View KFG5616Q1A-PEB6_3462338.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

onenand256(kfg5616x1a-xxb6) flash memory 1 onenand tm specification density part no. v cc (core & io) temperature pkg 256mb kfg5616q1a-deb6 1.8v(1.7v~1.95v) extended 67fbga(lf) KFG5616Q1A-PEB6 1.8v(1.7v~1.95v) extended 48tsop1 kfg5616d1a-deb6 2.65v(2.4v~2.9v) extended 67fbga(lf) kfg5616d1a-peb6 2.65v(2.4v~2.9v) extended 48tsop1 kfg5616u1a-dib6 3.3v(2.7v~3.6v) industrial 67fbga(lf) kfg5616u1a-pib6 3.3v(2.7v~3.6v) industrial 48tsop1 version: ver. 1.1 date: aug 12, 2005
onenand256(kfg5616x1a-xxb6) flash memory 2 this specification contains information about the samsung electronics company onenand ? ? flash memory product family. section 1.0 includes a general overview , revision history, and product ordering information. section 2.0 describes the onenand device. section 3.0 provides information about device operation. electrical specifications an d timing waveforms are in sections 4.0 though 6.0. section 7.0 provides additional appl ication and technical notes pertaining to use of the onenand. package dimensions are found in section 8.0 information in this document is provid ed in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or phys ical harm, or any military or defense application, or any governmental pr ocurement to which special terms or provisions may apply. onenand ? ? is a trademark of samsung electronics company, ltd. other names and brands may be claimed as the property of their rightful owners. copyright ? 2005, samsung electronics company, ltd 1.0 introduction
onenand256(kfg5616x1a-xxb6) flash memory 3 document title onenand revision history revision no. 0.0 1.0 1.1 remark preliminary final final draft date april 17, 2005 may 17, 2005 aug 12, 2005 history 1. initial issue 1. corrected the errata 2. added data protection flow chart. 3. removed cache read operation. 4. added additional information on command register. 5. revised interrupt status register information. 6. added int pin schematic. 7. changed tpgm1 to 205 from 320us, tpgm2 to 220 from 350us. 8. revised ac/dc parameters 9. revised ecc bypass description 10. revised reset parameters and timing diagrams. 1. corrected the errata 2. revised invalid block table creation flow chart. 3. revised multi bloc k erase description. 4. revised reset mode operation. 1.1 revision history
onenand256(kfg5616x1a-xxb6) flash memory 4 samsung offers a variety of flash so lutions including na nd flash, onenand ? and nor flash. samsung offers flash products both component and a variety of card formats including rs-mmc, mmc, compactflash, and smartmedia. to determine which samsung flash product solution is best for your application, refer the product selector chart. application requires samsung flash products nand onenand ? nor fast random read ? fast sequential read ?? fast write/program ?? multi block erase ? (max 64 blocks) ? erase suspend/resume ?? copyback ? (edc) ? (ecc) lock/unlock/lock-tight ?? ecc external (hardware/software) internal x scalability ?? 1.3 ordering information 1.2 flash product type selector k f g 56 1 6 x 1 a - x x b 6 samsung onenand memory device type g : single chip density 56 : 256mb operating temperature range e = extended temp. (-30 c to 85 c) i = industrial temp. (-40 c to 85 c) page architecture 1 : 1kb page version a : 2nd generation product line desinator b : include bad block d : daisy sample operating voltage range q : 1.8v(1.7 v to 1.95v) d : 2.65v(2.4v to 2.9v) u : 3.3v(2.7 v to 3.6v) package d : fbga(lead free) p : tsop(lead free) organization x16 organization speed 5 : 54mhz 6 : 66mhz
onenand256(kfg5616x1a-xxb6) flash memory 5 the attached datasheets are prepared and approved by samsung elec tronics. samsung electronics co., ltd. reserve the right to change the specifications. sams ung electronics will evaluate and reply to y our requests and questions about device. if you h ave any questions, please c ontact the samsung branch office near you. onenand is a highly integrated non-volatile memory solution based around a nand flash memory array. the chip integrates system features including: ? a bootram and bootloader ? two independent bi-directional 1kb dataram buffers ? a high-speed x16 host interface ? on-chip error correction ? on-chip nor interface controller this on-chip integration enables system designers to reduce exte rnal system logic and use high- density nand flash in applicatio ns that would otherwise have to use more nor components. onenand takes advantage of the higher performance nand program time, low power, and high density and combines it with the synchronous read performance of nor. the no r flash host interface makes onenand an i deal solution for appl ications like g3 smart phones, camera phones, and mobile applications that have large, advanced multimedia applic ations and operating systems, but lack a nand controller. when integrated into a samsung multi-chip-package with samsun g mobile ddr sdram, designers can complete a high-perfor- mance, small footprint solution. 1.4 architectural benefits
onenand256(kfg5616x1a-xxb6) flash memory 6 1.5 product features device architecture ? design technology: ? supply voltage: ? host interface: ? 3kb internal bufferram: ? slc nand array: device performance ? host interface type: - up to 66mhz clock frequen cy - linear burst 4-, 8-, 16, 32-words with wrap around - continuous 512 word seque ntial burst ? programmable burst read latency ? multiple sector read: ? multiple reset modes: ? multi block erase ? low power dissipation: - standby current : 10 a @1.8v device 25 a @2.65v/3.3v device - synchronous burst read current(66mhz) : 15ma@1.8v device 20ma@2.65v/3.3v device - load current : 30ma@1.8v device, 30ma@2.65v/3.3v device - program current : 25ma@1.8v device, 28ma@2.65v/3.3v device - erase current : 20ma@1.8v device, 23ma@2.65v/3.3v device - multi block erase current : 20ma@1.8v device, 23ma@2.65v/3.3v device system hardware ? voltage detector generating internal reset signal from vcc ? hardware reset input (rp ) ? data protection modes ? user-controlled one time programmable(otp) area ? internal 2bit edc / 1bit ecc ? internal bootloader supports booting solution in system ? handshaking feature ? detailed chip information packaging ? 256mb products 90nm 1.8v (1.7v ~ 1.95v), 2.65v (2.4 ~ 2.9v), 3.3v (2.7 ~3.6v) 16 bit 1kb bootram, 2kb dataram (1k+32)b page size, (64k+2k)b block size synchronous burst read asynchronous random read - 76ns access time asynchronous random write latency 3(up to 40mhz), 4, 5, 6, and 7 up to 2 sectors using sector count register cold/warm/hot/nand flash core resets up to 64 blocks typical power, - write protection for bootram - write protection for nand flash array - write protection during power-up - write protection during power-down - int pin indicates ready / busy - polling the interrupt register status bit - by id register 67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch fbga 48 tsop 1, 12mm x 20mm, 0.5mm pitch
onenand256(kfg5616x1a-xxb6) flash memory 7 onenand ? ? is a monolithic integrated circuit with a nand flash arra y using a nor flash interface. this device includes control logic, a nand flash array, and 3kb of internal bufferram. the bufferram reserves 1kb for boot code buffering (bootram) and 2kb for data buffering (dataram), split between 2 independent buffers. it has a x16 host interface and a random access time speed o f ~76ns. the device operates up to a maximum host-dr iven clock frequency of 66mhz fo r synchronous reads at vcc( or vccq. refer to chapter 4.2) with minimum 4-clock latency. below 40m hz it is accessible with minimum 3-clock la tency. appropriate wait cycles are dete r- mined by programmable read latency. onenand provides for multiple sector re ad operations by assigning the number of se ctors to be read in the sector counter register. the device includes one block-sized otp (one time programmable) area that can be used to increase system security or to provide identific ation capabilities. 1.6 general overview
onenand256(kfg5616x1a-xxb6) flash memory 8 2.1 detailed product description the onenand is an advanced generation, hi gh-performance nand-based flash memory. it integrates on-chip a single-level-cell (slc) nand flash arra y memory with two independent data buffers, boot ram buffer, a p age buffer for the flash array, and a one-time-programmable block. the combination of these memory areas enabl e high-speed pipelining of reads from host , bufferram , page buffer , and nand flash array memory. clock speeds up to 66mhz with a x16 wi de i/o yields a 54mbyte/second bandwidth. the onenand also includes a boot ram and boot loader. this enables the device to efficiently load boot code at device startup f rom the nand array without the need for off-chip boot device. one block of the nand array is set aside as an otp memory area. this area, available to the user, can be configured and locked with secured user information. on-chip controller interfaces ena ble the device to operate in systems without nand host controllers. 2.0 device description
onenand256(kfg5616x1a-xxb6) flash memory 9 b (capital letter) byte, 8bits w (capital letter) word, 16bits b (lower-case letter) bit ecc error correction code calculated ecc ecc that has been calculated during a load or program access written ecc ecc that has been stored as data in the nand flash array or in the bufferram bufferram on-chip internal buffer consisting of bootram and dataram bootram a 1kb portion of the bufferram reserved for boot code buffering dataram a 2kb portion of the bufferram reserved for data buffering sector part of a page of which 512b is the main data area and 16b is the spare data area. it is also the minimum load/pr ogram/copy-back program unit during a 1~2 sector operation is available. data unit possible data unit to be read from memory to bufferram or to be programmed to memory. - 528b of which 512b is in main area and 16b in spare area - 1056b of which 1024b is in main area and 32b in spare area 2.2 definitions
onenand256(kfg5616x1a-xxb6) flash memory 10 2.3.1 48tsop1 2.3 pin configuration (top view, facing down) tsop1 onenand chip 48pin, 12mm x 20mm, 0.5mm pitch tsop1 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c a15 a14 a13 a12 a11 a10 a9 a8 we v ss v cc int avd rp a7 a6 a5 a4 a3 a2 a1 a0 n.c v ss oe dq15 dq7 dq14 dq6 v ss dq13 dq5 dq12 dq4 dq11 dq3 dq10 dq2 v cc q dq9 dq1 dq8 dq0 rdy clk ce v cc 0.5mm pitch
onenand256(kfg5616x1a-xxb6) flash memory 11 (top view, balls facing down) 67ball fbga onenand chip 67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch fbga nc nc int a0 a1 nc a10 a6 nc nc we rp dq14 v ss v ss dq13 dq12 dq8 dq1 oe dq9 v cc dq7 dq4 dq11 dq10 dq3 v cc dq15 a12 dq0 dq5 dq6 ce dq2 nc nc a9 avd a7 a11 a8 a4 a5 a2 a3 nc core io clk a15 a13 a14 rdy nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 2.3.2 67ball fbga
onenand256(kfg5616x1a-xxb6) flash memory 12 note: do not leave power supply(vcc-core/vcc-io, v ss ) disconnected. pin name type nameand description host interface a15~a0 i address inputs - inputs for addresses during read and write operation, which are for addressing bufferram & register. dq15~dq0 i/o data inputs/outputs - inputs data during program and commands for all operations, outputs data during memory array/ register read cycles. data pins float to high-impedance when t he chip is deselected or outputs are disabled. int o interrupt notifying host when a command has completed. it is open drain output with internal resister (~50k ohm). after power up, it is at hi-z state. and after iobe is set to 1, it does not turn to hi-z condition when the chip is deselected or when outputs are disabled. rdy o ready indicates data valid in synchronous read modes and is activated while ce is low clk i clock clk synchronizes the device to the syst em bus frequency in synchronous read mode. the first rising edge of clk in conjunction with avd low latches address input. we i write enable we controls writes to the bufferram and registers. datas are latched on the we pulse?s rising edge avd i address valid detect indicates valid address presence on address inputs. during asynchronous read operation, all addresses are latched on avd ?s rising edge, and during synchronous read operation, all addresses are latched on clk?s rising edge while avd is held low for one clock cycle. > low : for asynchronous mode, indicates valid address ;for burst mode, causes starting address to be latched on rising edge on clk > high : device ignores address inputs rp i reset pin when low, rp resets internal operation of onenand. rp status is don?t care during power-up and bootloading. ce i chip enable ce -low activates internal control logic, and ce -high deselects the device, places it in standby state, and places dq in hi-z oe i output enable oe -low enables the device?s output data buffers during a read cycle. power supply v cc -core / vcc power for onenand core this is the power s upply for onenand core. v cc -io / vccq power for onenand i/o this is the power supply for onenand i/o vcc-io / vccq is internally se parated from vcc-core / vcc. v ss ground for onenand etc. dnu do not use leave it disconnected. these pins are used for testing. nc no connection lead is not internally connected. 2.4 pin description
onenand256(kfg5616x1a-xxb6) flash memory 13 2.6 memory array organization the onenand architecture integrates several memory areas on a single chip. 2.6.1 internal (nand arra y) memory organization the on-chip internal memory is a single-level-cell (slc) nand ar ray used for data storage and code. the internal memory is divi ded into a main area and a spare area. main area the main area is the primary memory array. this main area is divided into blocks of 64 pages. within a block, each page is 1k b and is comprised of 2 sectors. within a page, each sector is 512b and is comprised of 256 words. spare area the spare area is used for invalid block information and ecc stor age. spare area internal memory is associated with correspondi ng main area memory. within a block, each page has two 16b sect ors of spare area. each spare area sector is 8 words. 2.5 block diagram bootram host interface clk ce oe we rp avd statemachine bootloader internal registers (address/command/configuration /status registers) error correction logic int dataram0 bufferram nand flash array otp (one block) rdy a15~a0 dq15~dq0 dataram1
onenand256(kfg5616x1a-xxb6) flash memory 14 internal memory array information internal memory array organization area block page sector main 64kb 1kb 512b spare 2kb 32b 16b 1kb page0 512b 16b 32b page0 1kb page63 32b page63 sector main area spare area block page main area spare area 1kb 32b main area spare area 64kb 2kb page 0 page 63 512b sector0 512b sector1 16b sector0 16b sector1
onenand256(kfg5616x1a-xxb6) flash memory 15 the on-chip external memory is comprised of 3 buffers used for boot code storage and data buffering. the bootram is a 1kb buffer that receives boot code from the inte rnal memory and makes it available to the host at start up. there are two independent 1kb bi-directional data buffers, dataram0 and dataram1. these dual buffers enable the host to execute simultaneous read-while load, and write-while-program operations af ter boot up. during boot up, the bootram is used by the host to initialize the main memory, and deliver boot code from nand flash core to host. the external memory is divided into a main area and a sp are area. each buffer is the equivalent size of a sector. the main area data is 512b. the spare area data is 16b. external memory array information area bootram dataram0 dataram1 total size 1kb+32b 1kb+32b 1kb+32b number of sectors 2 2 2 sector main 512b 512b 512b spare 16b 16b 16b host otp block nand array boot code (1kb) bootram (1kb) dataram0 (1kb) dataram1 (1kb) external (bufferram) memory internal (nand array) memory 2.6.2 external (buffer ram) memory organization
onenand256(kfg5616x1a-xxb6) flash memory 16 external memory array organization bootram 0 bootram 1 bootram dataram 1_0 dataram 1_1 dataram1 { main area data spare area data dataram 0_0 dataram 0_1 dataram0 sector: (512 + 16) byte { (512b) (16b)
onenand256(kfg5616x1a-xxb6) flash memory 17 the following tables are the memory maps for the onenand. 2.7.1 internal (nand arr ay) memory organization 2.7 memory map the following tables show the internal memory address map in word order. note 1) the 2nd bit of page and sector address register is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block0 0000h 0000h~00fdh 64kb block32 0020h 0000h~00fdh 64kb block1 0001h 0000h~00fdh 64kb block33 0021h 0000h~00fdh 64kb block2 0002h 0000h~00fdh 64kb block34 0022h 0000h~00fdh 64kb block3 0003h 0000h~00fdh 64kb block35 0023h 0000h~00fdh 64kb block4 0004h 0000h~00fdh 64kb block36 0024h 0000h~00fdh 64kb block5 0005h 0000h~00fdh 64kb block37 0025h 0000h~00fdh 64kb block6 0006h 0000h~00fdh 64kb block38 0026h 0000h~00fdh 64kb block7 0007h 0000h~00fdh 64kb block39 0027h 0000h~00fdh 64kb block8 0008h 0000h~00fdh 64kb block40 0028h 0000h~00fdh 64kb block9 0009h 0000h~00fdh 64kb block41 0029h 0000h~00fdh 64kb block10 000ah 0000h~00fdh 64kb block42 002ah 0000h~00fdh 64kb block11 000bh 0000h~00fdh 64kb block43 002bh 0000h~00fdh 64kb block12 000ch 0000h~00fdh 64kb block44 002ch 0000h~00fdh 64kb block13 000dh 0000h~00fdh 64kb block45 002dh 0000h~00fdh 64kb block14 000eh 0000h~00fdh 64kb block46 002eh 0000h~00fdh 64kb block15 000fh 0000h~00fdh 64kb block47 002fh 0000h~00fdh 64kb block16 0010h 0000h~00fdh 64kb block48 0030h 0000h~00fdh 64kb block17 0011h 0000h~00fdh 64kb block49 0031h 0000h~00fdh 64kb block18 0012h 0000h~00fdh 64kb block50 0032h 0000h~00fdh 64kb block19 0013h 0000h~00fdh 64kb block51 0033h 0000h~00fdh 64kb block20 0014h 0000h~00fdh 64kb block52 0034h 0000h~00fdh 64kb block21 0015h 0000h~00fdh 64kb block53 0035h 0000h~00fdh 64kb block22 0016h 0000h~00fdh 64kb block54 0036h 0000h~00fdh 64kb block23 0017h 0000h~00fdh 64kb block55 0037h 0000h~00fdh 64kb block24 0018h 0000h~00fdh 64kb block56 0038h 0000h~00fdh 64kb block25 0019h 0000h~00fdh 64kb block57 0039h 0000h~00fdh 64kb block26 001ah 0000h~00fdh 64kb block58 003ah 0000h~00fdh 64kb block27 001bh 0000h~00fdh 64kb block59 003bh 0000h~00fdh 64kb block28 001ch 0000h~00fdh 64kb block60 003ch 0000h~00fdh 64kb block29 001dh 0000h~00fdh 64kb block61 003dh 0000h~00fdh 64kb block30 001eh 0000h~00fdh 64kb block62 003eh 0000h~00fdh 64kb block31 001fh 0000h~00fdh 64kb block63 003fh 0000h~00fdh 64kb
onenand256(kfg5616x1a-xxb6) flash memory 18 note 1) 2nd bit of page and sector address is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block64 0040h 0000h~00fdh 64kb block96 0060h 0000h~00fdh 64kb block65 0041h 0000h~00fdh 64kb block97 0061h 0000h~00fdh 64kb block66 0042h 0000h~00fdh 64kb block98 0062h 0000h~00fdh 64kb block67 0043h 0000h~00fdh 64kb block99 0063h 0000h~00fdh 64kb block68 0044h 0000h~00fdh 64kb block100 0064h 0000h~00fdh 64kb block69 0045h 0000h~00fdh 64kb block101 0065h 0000h~00fdh 64kb block70 0046h 0000h~00fdh 64kb block102 0066h 0000h~00fdh 64kb block71 0047h 0000h~00fdh 64kb block103 0067h 0000h~00fdh 64kb block72 0048h 0000h~00fdh 64kb block104 0068h 0000h~00fdh 64kb block73 0049h 0000h~00fdh 64kb block105 0069h 0000h~00fdh 64kb block74 004ah 0000h~00fdh 64kb block106 006ah 0000h~00fdh 64kb block75 004bh 0000h~00fdh 64kb block107 006bh 0000h~00fdh 64kb block76 004ch 0000h~00fdh 64kb block108 006ch 0000h~00fdh 64kb block77 004dh 0000h~00fdh 64kb block109 006dh 0000h~00fdh 64kb block78 004eh 0000h~00fdh 64kb block110 006eh 0000h~00fdh 64kb block79 004fh 0000h~00fdh 64kb block111 006fh 0000h~00fdh 64kb block80 0050h 0000h~00fdh 64kb block112 0070h 0000h~00fdh 64kb block81 0051h 0000h~00fdh 64kb block113 0071h 0000h~00fdh 64kb block82 0052h 0000h~00fdh 64kb block114 0072h 0000h~00fdh 64kb block83 0053h 0000h~00fdh 64kb block115 0073h 0000h~00fdh 64kb block84 0054h 0000h~00fdh 64kb block116 0074h 0000h~00fdh 64kb block85 0055h 0000h~00fdh 64kb block117 0075h 0000h~00fdh 64kb block86 0056h 0000h~00fdh 64kb block118 0076h 0000h~00fdh 64kb block87 0057h 0000h~00fdh 64kb block119 0077h 0000h~00fdh 64kb block88 0058h 0000h~00fdh 64kb block120 0078h 0000h~00fdh 64kb block89 0059h 0000h~00fdh 64kb block121 0079h 0000h~00fdh 64kb block90 005ah 0000h~00fdh 64kb block122 007ah 0000h~00fdh 64kb block91 005bh 0000h~00fdh 64kb block123 007bh 0000h~00fdh 64kb block92 005ch 0000h~00fdh 64kb block124 007ch 0000h~00fdh 64kb block93 005dh 0000h~00fdh 64kb block125 007dh 0000h~00fdh 64kb block94 005eh 0000h~00fdh 64kb block126 007eh 0000h~00fdh 64kb block95 005fh 0000h~00fdh 64kb block127 007fh 0000h~00fdh 64kb
onenand256(kfg5616x1a-xxb6) flash memory 19 note 1) 2nd bit of page and sector address is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block128 0080h 0000h~00fdh 64kb block160 00a0h 0000h~00fdh 64kb block129 0081h 0000h~00fdh 64kb block161 00a1h 0000h~00fdh 64kb block130 0082h 0000h~00fdh 64kb block162 00a2h 0000h~00fdh 64kb block131 0083h 0000h~00fdh 64kb block163 00a3h 0000h~00fdh 64kb block132 0084h 0000h~00fdh 64kb block164 00a4h 0000h~00fdh 64kb block133 0085h 0000h~00fdh 64kb block165 00a5h 0000h~00fdh 64kb block134 0086h 0000h~00fdh 64kb block166 00a6h 0000h~00fdh 64kb block135 0087h 0000h~00fdh 64kb block167 00a7h 0000h~00fdh 64kb block136 0088h 0000h~00fdh 64kb block168 00a8h 0000h~00fdh 64kb block137 0089h 0000h~00fdh 64kb block169 00a9h 0000h~00fdh 64kb block138 008ah 0000h~00fdh 64kb block170 00aah 0000h~00fdh 64kb block139 008bh 0000h~00fdh 64kb block171 00abh 0000h~00fdh 64kb block140 008ch 0000h~00fdh 64kb block172 00ach 0000h~00fdh 64kb block141 008dh 0000h~00fdh 64kb block173 00adh 0000h~00fdh 64kb block142 008eh 0000h~00fdh 64kb block174 00aeh 0000h~00fdh 64kb block143 008fh 0000h~00fdh 64kb block175 00afh 0000h~00fdh 64kb block144 0090h 0000h~00fdh 64kb block176 00b0h 0000h~00fdh 64kb block145 0091h 0000h~00fdh 64kb block177 00b1h 0000h~00fdh 64kb block146 0092h 0000h~00fdh 64kb block178 00b2h 0000h~00fdh 64kb block147 0093h 0000h~00fdh 64kb block179 00b3h 0000h~00fdh 64kb block148 0094h 0000h~00fdh 64kb block180 00b4h 0000h~00fdh 64kb block149 0095h 0000h~00fdh 64kb block181 00b5h 0000h~00fdh 64kb block150 0096h 0000h~00fdh 64kb block182 00b6h 0000h~00fdh 64kb block151 0097h 0000h~00fdh 64kb block183 00b7h 0000h~00fdh 64kb block152 0098h 0000h~00fdh 64kb block184 00b8h 0000h~00fdh 64kb block153 0099h 0000h~00fdh 64kb block185 00b9h 0000h~00fdh 64kb block154 009ah 0000h~00fdh 64kb block186 00bah 0000h~00fdh 64kb block155 009bh 0000h~00fdh 64kb block187 00bbh 0000h~00fdh 64kb block156 009ch 0000h~00fdh 64kb block188 00bch 0000h~00fdh 64kb block157 009dh 0000h~00fdh 64kb block189 00bdh 0000h~00fdh 64kb block158 009eh 0000h~00fdh 64kb block190 00beh 0000h~00fdh 64kb block159 009fh 0000h~00fdh 64kb block191 00bfh 0000h~00fdh 64kb
onenand256(kfg5616x1a-xxb6) flash memory 20 note 1) 2nd bit of page and sector address is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block192 00c0h 0000h~00fdh 64kb block224 00e0h 0000h~00fdh 64kb block193 00c1h 0000h~00fdh 64kb block225 00e1h 0000h~00fdh 64kb block194 00c2h 0000h~00fdh 64kb block226 00e2h 0000h~00fdh 64kb block195 00c3h 0000h~00fdh 64kb block227 00e3h 0000h~00fdh 64kb block196 00c4h 0000h~00fdh 64kb block228 00e4h 0000h~00fdh 64kb block197 00c5h 0000h~00fdh 64kb block229 00e5h 0000h~00fdh 64kb block198 00c6h 0000h~00fdh 64kb block230 00e6h 0000h~00fdh 64kb block199 00c7h 0000h~00fdh 64kb block231 00e7h 0000h~00fdh 64kb block200 00c8h 0000h~00fdh 64kb block232 00e8h 0000h~00fdh 64kb block201 00c9h 0000h~00fdh 64kb block233 00e9h 0000h~00fdh 64kb block202 00cah 0000h~00fdh 64kb block234 00eah 0000h~00fdh 64kb block203 00cbh 0000h~00fdh 64kb block235 00ebh 0000h~00fdh 64kb block204 00cch 0000h~00fdh 64kb block236 00ech 0000h~00fdh 64kb block205 00cdh 0000h~00fdh 64kb block237 00edh 0000h~00fdh 64kb block206 00ceh 0000h~00fdh 64kb block238 00eeh 0000h~00fdh 64kb block207 00cfh 0000h~00fdh 64kb block239 00efh 0000h~00fdh 64kb block208 00d0h 0000h~00fdh 64kb block240 00f0h 0000h~00fdh 64kb block209 00d1h 0000h~00fdh 64kb block241 00f1h 0000h~00fdh 64kb block210 00d2h 0000h~00fdh 64kb block242 00f2h 0000h~00fdh 64kb block211 00d3h 0000h~00fdh 64kb block243 00f3h 0000h~00fdh 64kb block212 00d4h 0000h~00fdh 64kb block244 00f4h 0000h~00fdh 64kb block213 00d5h 0000h~00fdh 64kb block245 00f5h 0000h~00fdh 64kb block214 00d6h 0000h~00fdh 64kb block246 00f6h 0000h~00fdh 64kb block215 00d7h 0000h~00fdh 64kb block247 00f7h 0000h~00fdh 64kb block216 00d8h 0000h~00fdh 64kb block248 00f8h 0000h~00fdh 64kb block217 00d9h 0000h~00fdh 64kb block249 00f9h 0000h~00fdh 64kb block218 00dah 0000h~00fdh 64kb block250 00fah 0000h~00fdh 64kb block219 00dbh 0000h~00fdh 64kb block251 00fbh 0000h~00fdh 64kb block220 00dch 0000h~00fdh 64kb block252 00fch 0000h~00fdh 64kb block221 00ddh 0000h~00fdh 64kb block253 00fdh 0000h~00fdh 64kb block222 00deh 0000h~00fdh 64kb block254 00feh 0000h~00fdh 64kb block223 00dfh 0000h~00fdh 64kb block255 00ffh 0000h~00fdh 64kb
onenand256(kfg5616x1a-xxb6) flash memory 21 note 1) 2nd bit of page and sector address is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block256 0100h 0000h~00fdh 64kb block288 0120h 0000h~00fdh 64kb block257 0101h 0000h~00fdh 64kb block289 0121h 0000h~00fdh 64kb block258 0102h 0000h~00fdh 64kb block290 0122h 0000h~00fdh 64kb block259 0103h 0000h~00fdh 64kb block291 0123h 0000h~00fdh 64kb block260 0104h 0000h~00fdh 64kb block292 0124h 0000h~00fdh 64kb block261 0105h 0000h~00fdh 64kb block293 0125h 0000h~00fdh 64kb block262 0106h 0000h~00fdh 64kb block294 0126h 0000h~00fdh 64kb block263 0107h 0000h~00fdh 64kb block295 0127h 0000h~00fdh 64kb block264 0108h 0000h~00fdh 64kb block296 0128h 0000h~00fdh 64kb block265 0109h 0000h~00fdh 64kb block297 0129h 0000h~00fdh 64kb block266 010ah 0000h~00fdh 64kb block298 012ah 0000h~00fdh 64kb block267 010bh 0000h~00fdh 64kb block299 012bh 0000h~00fdh 64kb block268 010ch 0000h~00fdh 64kb block300 012ch 0000h~00fdh 64kb block269 010dh 0000h~00fdh 64kb block301 012dh 0000h~00fdh 64kb block270 010eh 0000h~00fdh 64kb block302 012eh 0000h~00fdh 64kb block271 010fh 0000h~00fdh 64kb block303 012fh 0000h~00fdh 64kb block272 0110h 0000h~00fdh 64kb block304 0130h 0000h~00fdh 64kb block273 0111h 0000h~00fdh 64kb block305 0131h 0000h~00fdh 64kb block274 0112h 0000h~00fdh 64kb block306 0132h 0000h~00fdh 64kb block275 0113h 0000h~00fdh 64kb block307 0133h 0000h~00fdh 64kb block276 0114h 0000h~00fdh 64kb block308 0134h 0000h~00fdh 64kb block277 0115h 0000h~00fdh 64kb block309 0135h 0000h~00fdh 64kb block278 0116h 0000h~00fdh 64kb block310 0136h 0000h~00fdh 64kb block279 0117h 0000h~00fdh 64kb block311 0137h 0000h~00fdh 64kb block280 0118h 0000h~00fdh 64kb block312 0138h 0000h~00fdh 64kb block281 0119h 0000h~00fdh 64kb block313 0139h 0000h~00fdh 64kb block282 011ah 0000h~00fdh 64kb block314 013ah 0000h~00fdh 64kb block283 011bh 0000h~00fdh 64kb block315 013bh 0000h~00fdh 64kb block284 011ch 0000h~00fdh 64kb block316 013ch 0000h~00fdh 64kb block285 011dh 0000h~00fdh 64kb block317 013dh 0000h~00fdh 64kb block286 011eh 0000h~00fdh 64kb block318 013eh 0000h~00fdh 64kb block287 011fh 0000h~00fdh 64kb block319 013fh 0000h~00fdh 64kb
onenand256(kfg5616x1a-xxb6) flash memory 22 note 1) 2nd bit of page and sector address is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block320 0140h 0000h~00fdh 64kb block352 0160h 0000h~00fdh 64kb block321 0141h 0000h~00fdh 64kb block353 0161h 0000h~00fdh 64kb block322 0142h 0000h~00fdh 64kb block354 0162h 0000h~00fdh 64kb block323 0143h 0000h~00fdh 64kb block355 0163h 0000h~00fdh 64kb block324 0144h 0000h~00fdh 64kb block356 0164h 0000h~00fdh 64kb block325 0145h 0000h~00fdh 64kb block357 0165h 0000h~00fdh 64kb block326 0146h 0000h~00fdh 64kb block358 0166h 0000h~00fdh 64kb block327 0147h 0000h~00fdh 64kb block359 0167h 0000h~00fdh 64kb block328 0148h 0000h~00fdh 64kb block360 0168h 0000h~00fdh 64kb block329 0149h 0000h~00fdh 64kb block361 0169h 0000h~00fdh 64kb block330 014ah 0000h~00fdh 64kb block362 016ah 0000h~00fdh 64kb block331 014bh 0000h~00fdh 64kb block363 016bh 0000h~00fdh 64kb block332 014ch 0000h~00fdh 64kb block364 016ch 0000h~00fdh 64kb block333 014dh 0000h~00fdh 64kb block365 016dh 0000h~00fdh 64kb block334 014eh 0000h~00fdh 64kb block366 016eh 0000h~00fdh 64kb block335 014fh 0000h~00fdh 64kb block367 016fh 0000h~00fdh 64kb block336 0150h 0000h~00fdh 64kb block368 0170h 0000h~00fdh 64kb block337 0151h 0000h~00fdh 64kb block369 0171h 0000h~00fdh 64kb block338 0152h 0000h~00fdh 64kb block370 0172h 0000h~00fdh 64kb block339 0153h 0000h~00fdh 64kb block371 0173h 0000h~00fdh 64kb block340 0154h 0000h~00fdh 64kb block372 0174h 0000h~00fdh 64kb block341 0155h 0000h~00fdh 64kb block373 0175h 0000h~00fdh 64kb block342 0156h 0000h~00fdh 64kb block374 0176h 0000h~00fdh 64kb block343 0157h 0000h~00fdh 64kb block375 0177h 0000h~00fdh 64kb block344 0158h 0000h~00fdh 64kb block376 0178h 0000h~00fdh 64kb block345 0159h 0000h~00fdh 64kb block377 0179h 0000h~00fdh 64kb block346 015ah 0000h~00fdh 64kb block378 017ah 0000h~00fdh 64kb block347 015bh 0000h~00fdh 64kb block379 017bh 0000h~00fdh 64kb block348 015ch 0000h~00fdh 64kb block380 017ch 0000h~00fdh 64kb block349 015dh 0000h~00fdh 64kb block381 017dh 0000h~00fdh 64kb block350 015eh 0000h~00fdh 64kb block382 017eh 0000h~00fdh 64kb block351 015fh 0000h~00fdh 64kb block383 017fh 0000h~00fdh 64kb
onenand256(kfg5616x1a-xxb6) flash memory 23 note 1) 2nd bit of page and sector address is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block384 0180h 0000h~00fdh 64kb block416 01a0h 0000h~00fdh 64kb block385 0181h 0000h~00fdh 64kb block417 01a1h 0000h~00fdh 64kb block386 0182h 0000h~00fdh 64kb block418 01a2h 0000h~00fdh 64kb block387 0183h 0000h~00fdh 64kb block419 01a3h 0000h~00fdh 64kb block388 0184h 0000h~00fdh 64kb block420 01a4h 0000h~00fdh 64kb block389 0185h 0000h~00fdh 64kb block421 01a5h 0000h~00fdh 64kb block390 0186h 0000h~00fdh 64kb block422 01a6h 0000h~00fdh 64kb block391 0187h 0000h~00fdh 64kb block423 01a7h 0000h~00fdh 64kb block392 0188h 0000h~00fdh 64kb block424 01a8h 0000h~00fdh 64kb block393 0189h 0000h~00fdh 64kb block425 01a9h 0000h~00fdh 64kb block394 018ah 0000h~00fdh 64kb block426 01aah 0000h~00fdh 64kb block395 018bh 0000h~00fdh 64kb block427 01abh 0000h~00fdh 64kb block396 018ch 0000h~00fdh 64kb block428 01ach 0000h~00fdh 64kb block397 018dh 0000h~00fdh 64kb block429 01adh 0000h~00fdh 64kb block398 018eh 0000h~00fdh 64kb block430 01aeh 0000h~00fdh 64kb block399 018fh 0000h~00fdh 64kb block431 01afh 0000h~00fdh 64kb block400 0190h 0000h~00fdh 64kb block432 01b0h 0000h~00fdh 64kb block401 0191h 0000h~00fdh 64kb block433 01b1h 0000h~00fdh 64kb block402 0192h 0000h~00fdh 64kb block434 01b2h 0000h~00fdh 64kb block403 0193h 0000h~00fdh 64kb block435 01b3h 0000h~00fdh 64kb block404 0194h 0000h~00fdh 64kb block436 01b4h 0000h~00fdh 64kb block405 0195h 0000h~00fdh 64kb block437 01b5h 0000h~00fdh 64kb block406 0196h 0000h~00fdh 64kb block438 01b6h 0000h~00fdh 64kb block407 0197h 0000h~00fdh 64kb block439 01b7h 0000h~00fdh 64kb block408 0198h 0000h~00fdh 64kb block440 01b8h 0000h~00fdh 64kb block409 0199h 0000h~00fdh 64kb block441 01b9h 0000h~00fdh 64kb block410 019ah 0000h~00fdh 64kb block442 01bah 0000h~00fdh 64kb block411 019bh 0000h~00fdh 64kb block443 01bbh 0000h~00fdh 64kb block412 019ch 0000h~00fdh 64kb block444 01bch 0000h~00fdh 64kb block413 019dh 0000h~00fdh 64kb block445 01bdh 0000h~00fdh 64kb block414 019eh 0000h~00fdh 64kb block446 01beh 0000h~00fdh 64kb block415 019fh 0000h~00fdh 64kb block447 01bfh 0000h~00fdh 64kb
onenand256(kfg5616x1a-xxb6) flash memory 24 note 1) 2nd bit of page and sector address is don?t care. so the address range is bigger than the real range. even though 2nd bit is set to "1", this bit is always considered "0". please refer to start address 8 register. block block address page and sector address (1) size block block address page and sector address (1) size block448 01c0h 0000h~00fdh 64kb block480 01e0h 0000h~00fdh 64kb block449 01c1h 0000h~00fdh 64kb block481 01e1h 0000h~00fdh 64kb block450 01c2h 0000h~00fdh 64kb block482 01e2h 0000h~00fdh 64kb block451 01c3h 0000h~00fdh 64kb block483 01e3h 0000h~00fdh 64kb block452 01c4h 0000h~00fdh 64kb block484 01e4h 0000h~00fdh 64kb block453 01c5h 0000h~00fdh 64kb block485 01e5h 0000h~00fdh 64kb block454 01c6h 0000h~00fdh 64kb block486 01e6h 0000h~00fdh 64kb block455 01c7h 0000h~00fdh 64kb block487 01e7h 0000h~00fdh 64kb block456 01c8h 0000h~00fdh 64kb block488 01e8h 0000h~00fdh 64kb block457 01c9h 0000h~00fdh 64kb block489 01e9h 0000h~00fdh 64kb block458 01cah 0000h~00fdh 64kb block490 01eah 0000h~00fdh 64kb block459 01cbh 0000h~00fdh 64kb block491 01ebh 0000h~00fdh 64kb block460 01cch 0000h~00fdh 64kb block492 01ech 0000h~00fdh 64kb block461 01cdh 0000h~00fdh 64kb block493 01edh 0000h~00fdh 64kb block462 01ceh 0000h~00fdh 64kb block494 01eeh 0000h~00fdh 64kb block463 01cfh 0000h~00fdh 64kb block495 01efh 0000h~00fdh 64kb block464 01d0h 0000h~00fdh 64kb block496 01f0h 0000h~00fdh 64kb block465 01d1h 0000h~00fdh 64kb block497 01f1h 0000h~00fdh 64kb block466 01d2h 0000h~00fdh 64kb block498 01f2h 0000h~00fdh 64kb block467 01d3h 0000h~00fdh 64kb block499 01f3h 0000h~00fdh 64kb block468 01d4h 0000h~00fdh 64kb block500 01f4h 0000h~00fdh 64kb block469 01d5h 0000h~00fdh 64kb block501 01f5h 0000h~00fdh 64kb block470 01d6h 0000h~00fdh 64kb block502 01f6h 0000h~00fdh 64kb block471 01d7h 0000h~00fdh 64kb block503 01f7h 0000h~00fdh 64kb block472 01d8h 0000h~00fdh 64kb block504 01f8h 0000h~00fdh 64kb block473 01d9h 0000h~00fdh 64kb block505 01f9h 0000h~00fdh 64kb block474 01dah 0000h~00fdh 64kb block506 01fah 0000h~00fdh 64kb block475 01dbh 0000h~00fdh 64kb block507 01fbh 0000h~00fdh 64kb block476 01dch 0000h~00fdh 64kb block508 01fch 0000h~00fdh 64kb block477 01ddh 0000h~00fdh 64kb block509 01fdh 0000h~00fdh 64kb block478 01deh 0000h~00fdh 64kb block510 01feh 0000h~00fdh 64kb block479 01dfh 0000h~00fdh 64kb block511 01ffh 0000h~00fdh 64kb
onenand256(kfg5616x1a-xxb6) flash memory 25 the figure below shows the assignment of the spare area in the internal memory nand array. spare area assignment in the internal memory nand array information word byte note description 1 lsb 1 invalid block information in 1st and 2nd page of an invalid block msb 2 lsb 2 managed by internal ecc logic for logical sector number data msb 3 lsb msb 3 reserved for future use 4 lsb msb 5 lsb dedicated to internal ecc logic. read only. eccm 1st for main area data msb dedicated to internal ecc logic. read only. eccm 2nd for main area data 6 lsb dedicated to internal ecc logic. read only. eccm 3rd for main area data msb dedicated to internal ecc logic. read only. eccs 1st for 2nd word of spare area data 7 lsb dedicated to internal ecc logic. read only. eccs 2nd for 3rd word of spare area data msb 3 reserved for future use 8 lsb 4 available to the user msb { 1 st w eccm 1st eccm 2nd eccm 3rd eccs 1st eccs 2nd lsb msb lsb msb { 2 nd w lsb msb { 3 rd w lsb msb { 4 th w lsb msb { 5 th w lsb msb { 6 th w lsb msb { 7 th w lsb msb { 8 th w lsb msb note1 note1 note2 note2 note2 note3 note3 note3 note4 note4 (note3) 2.7.2 internal memory spare area assignment main area 256w main area 256w spare area 8w spare area 8w
onenand256(kfg5616x1a-xxb6) flash memory 26 the following table shows the external me mory address map in word and byte order. note that the data output is unknown while hos t reads a register bit of reserved area. 2.7.3 external memory (bufferram) address map division address (word order) address (byte order) size (total 128kb) usage description main area (64kb) 0000h~00ffh 00000h~001feh 512b 1kb bootm 0 bootram main sector0 0100h~01ffh 00200h~003feh 512b bootm 1 bootram main sector1 0200h~02ffh 00400h~005feh 512b 2kb datam 0_0 dataram main page0/sector0 0300h~03ffh 00600h~007feh 512b datam 0_1 dataram main page0/sector1 0400h~04ffh 00800h~009feh 512b datam 1_0 dataram main page1/sector0 0500h~05ffh 00a00h~00bfeh 512b datam 1_1 dataram main page1/sector1 0600h~7fffh 00c00h~0fffeh 61kb 61kb reserved reserved spare area (8kb) 8000h~8007h 10000h~1000eh 16b 32b boots 0 bootram spare sector0 8008h~800fh 10010h~1001eh 16b boots 1 bootram spare sector1 8010h~8017h 10020h~1002eh 16b 64b datas 0_0 dataram spare page0/sector0 8018h~801fh 10030h~1003eh 16b datas 0_1 dataram spare page0/sector1 8020h~8027h 10040h~1004eh 16b datas 1_0 dataram spare page1/sector0 8028h~802fh 10050h~1005eh 16b datas 1_1 dataram spare page1/sector1 8030h~8fffh 1006eh~11ffeh 8096b 8096b reserved reserved reserved (24kb) 9000h~bfffh 12000h~17ffeh 24kb 24kb reserved reserved reserved (8kb) c000h~cfffh 18000h~19ffeh 8kb 8kb reserved reserved reserved (16kb) d000h~efffh 1a000h~1dffeh 16kb 16kb reserved reserved registers (8kb) f000h~ffffh 1e000h~1fffeh 8kb 8kb registers registers
onenand256(kfg5616x1a-xxb6) flash memory 27 the tables below show word order address map inform ation for the bootram and dataram main and spare areas. 2.7.4 external memory map detail information -0000h~01ffh: 2(sector) x 512byte(nand main area) = 1kb 0000h~00ffh(512b) bootm 0 (sector 0 of page 0) 0100h~01ffh(512b) bootm 1 (sector 1 of page 0) ? bootram(main area) -0200h~05ffh: 4(sector) x 512byte(nand main area) = 2kb 0200h~02ffh(512b) datam 0_0 (sector 0 of page 0) 0300h~03ffh(512b) datam 0_1 (sector 1 of page 0) 0400h~04ffh(512b) datam 1_0 (sector 0 of page 1) 0500h~05ffh(512b) datam 1_1 (sector 1 of page 1) ? dataram(main area) -8000h~800fh: 2(sector) x 16byte(nand spare area) = 32b 8000h~8007h(16b) boots 0 (sector 0 of page 0) 8008h~800fh(16b) boots 1 (sector 1 of page 0) ? bootram(spare area) -8010h~802fh: 4(sector) x 16byte(nand spare area) = 64b *nand flash array consists of 1k b page size and 64kb block size. 8010h~8017h(16b) datas 0_0 (sector 0 of page 0) 8018h~801fh(16b) datas 0_1 (sector 1 of page 0) 8020h~8027h(16b) datas 1_0 (sector 0 of page 1) 8028h~802fh(16b) datas 1_1 (sector 1 of page 1) ? dataram(spare area)
onenand256(kfg5616x1a-xxb6) flash memory 28 2.7.5 external memory spare area assignment buf. word address byte address f e d c b a 9 8 7 6 5 4 3 2 1 0 boots 0 8000h 10000h bi 8001h 10002h managed by internal ecc logic 8002h 10004h reserved for the future use managed by internal ecc logic 8003h 10006h reserved for the current and future use 8004h 10008h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8005h 1000ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8006h 1000ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 8007h 1000eh free usage boots 1 8008h 10010h bi 8009h 10012h managed by internal ecc logic 800ah 10014h reserved for the future use managed by internal ecc logic 800bh 10016h reserved for the current and future use 800ch 10018h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 800dh 1001ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 800eh 1001ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 800fh 1001eh free usage datas 0_0 8010h 10020h bi 8011h 10022h managed by internal ecc logic 8012h 10024h reserved for the future use managed by internal ecc logic 8013h 10026h reserved for the current and future use 8014h 10028h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8015h 1002ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8016h 1002ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 8017h 1002eh free usage datas 0_1 8018h 10030h bi 8019h 10032h managed by internal ecc logic 801ah 10034h reserved for the future use managed by internal ecc logic 801bh 10036h reserved for the current and future use 801ch 10038h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 801dh 1003ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 801eh 1003ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 801fh 1003eh free usage equivalent to 1word of nand flash
onenand256(kfg5616x1a-xxb6) flash memory 29 note: - bi: invalid block information >host can use complete spare area exce pt bi and ecc code area. for example, host can write data to spare area buffer except for the area controlled by ecc logic at program operation. >in case of ?with ecc? mode, onenand automatically generates ecc code for both main and spare data of memory during program ope ration, but does not update ecc code to spare bufferram during load operation. >when loading/programming spare area, spare area bufferram address( bsa) and bufferram sector count(bsc) is chosen via start bu ffer register as it is. buf. word address byte address f e d c b a 9 8 7 6 5 4 3 2 1 0 datas 1_0 8020h 10040h bi 8021h 10042h managed by internal ecc logic 8022h 10044h reserved for the future use managed by internal ecc logic 8023h 10046h reserved for the current and future use 8024h 10048h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8025h 1004ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8026h 1004ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 8027h 1004eh free usage datas 1_1 8028h 10050h bi 8029h 10052h managed by internal ecc logic 802ah 10054h reserved for the future use managed by internal ecc logic 802bh 10056h reserved for the current and future use 802ch 10058h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 802dh 1005ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 802eh 1005ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 802fh 1005eh free usage equivalent to 1word of nand flash
onenand256(kfg5616x1a-xxb6) flash memory 30 section 2.8 of this specification provides information about the onenand registers. 2.8.1 regis ter address map 2.8 registers this map describes the register addresses, register name, register description, and host accessibility. address (word order) address (byte order) name host access description f000h 1e000h manufacturer id r manufacturer identification f001h 1e002h device id r device identification f002h 1e004h version id r n/a f003h 1e006h data buffer size r data buffer size f004h 1e008h boot buffer size r boot buffer size f005h 1e00ah amount of buffers r amount of data/boot buffers f006h 1e00ch technology r info about technology f007h~f0ffh 1e00eh~1e1feh reserved - reserved for user f100h 1e200h start address 1 r/w nand flash block address f101h 1e202h start address 2 r/w n/a f102h 1e204h start address 3 r/w destination block address for copy back program f103h 1e206h start address 4 r/w destination page & sector address for copy back program f104h 1e208h start address 5 - n/a f105h 1e20ah start address 6 - n/a f106h 1e20ch start address 7 - n/a f107h 1e20eh start address 8 r/w nand flash page & sector address f108h~f1ffh 1e210h~1e3feh reserved - reserved for user f200h 1e400h start buffer r/w buffer number for the page data transfer to/from the memory and the start buffer address the meaning is with which buffer to start and how many buffers to use for the data transfer f201h~f207h 1e402h~1e40eh reserved - reserved for user f208h~f21fh 1e410h~1e43eh reserved - rese rved for vendor specific purposes f220h 1e440h command r/w host control and memory operation commands f221h 1e442h system configuration 1 r, r/w memory and host interface configuration f222h 1e444h system configuration 2 -n/a f223h~f22fh 1e446h~1e45eh reserved - reserved for user f230h~f23fh 1e460h~1e47eh reserved - rese rved for vendor specific purposes f240h 1e480h controller status r controller status and result of memory operation f241h 1e482h interrupt r/w memory command completion interrupt status f242h~f24bh 1e484h~1e496h reserved - reserved for user f24ch 1e498h start block address r/w start memory block address in write protection mode
onenand256(kfg5616x1a-xxb6) flash memory 31 this read register describes the manufacturer's identification. samsung electronics company m anufacturer's id is 00ech. f000h, default = 00ech 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 manufid 2.8.2 manufacturer id register f000h (r) address (word order) address (byte order) name host access description f24dh 1e49ah reserved r/w reserved for user f24eh 1e49ch write protection status r current memory write protection status (unlocked/locked/tight-locked) f24fh~feffh 1e49eh~1fdfeh reserved - reserved for user ff00h 1fe00h ecc status register r ecc status of sector ff01h 1fe02h ecc result of main area data r ecc error position of main area data error for first selected sector ff02h 1fe04h ecc result of spare area data r ecc error position of spare area data error for first selected sector ff03h 1fe06h ecc result of main area data r ecc error position of main area data error for second selected sector ff04h 1fe08h ecc result of spare area data r ecc error position of spare area data error for second selected sector ff05h~ffffh 1fe0ah~1fffeh reserved - res erved for vendor specific purposes
onenand256(kfg5616x1a-xxb6) flash memory 32 this read register describes the device. f001h, see table for default. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 deviceid device identification device id default device identification description deviceid [1:0] vcc 00 = 1.8v, 01 = 2.65v/3.3v, 10/11 = reserved deviceid [2] muxed/demuxed 0 = muxed, 1 = demuxed deviceid [3] single/dpp 0 = single, 1 = ddp deviceid [7:4] density 0000 = 128mb, 0001 = 256mb, 0010 = 512mb, 0011 = 1gb, 0100 = 2gb, 0101=4gb deviceid [8] top/bottom boot 0 = bottom boot, 1 = top boot device deviceid[15:0] kfg5616q1a 0014h kfg5616d1a 0015h kfg5616u1a 0015h 2.8.3 device id register f001h (r)
onenand256(kfg5616x1a-xxb6) flash memory 33 2.8.5 data buffer size register f003h (r) this read register describes t he size of the data buffer. f003h, default = 0400h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 databufsize data buffer size information version identification description databufsize total data buffer size in words equal to 2 buffers of 512 words each (2 x 512 = 2 10 ) in the memory interface 2.8.4 version id register f002h this register is reserved for manufacturer this read register describes t he size of the boot buffer. f004h, default = 0200h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bootbufsize register information description bootbufsize total boot buffer size in words equal to 1 buffer of 512 words (1 x 512 = 2 9 ) in the memory interface 2.8.6 boot buffer size register f004h (r)
onenand256(kfg5616x1a-xxb6) flash memory 34 2.8.7 number of bu ffers register f005h (r) this read register describes the number of each buffer. f005h, default = 0201h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 databufamount bootbufamount number of buffers information register information description databufamount the number of data buffers = 2 (2 n , n=1) bootbufamount the number of boot buffers = 1 (2 n , n=0) this read register describes the internal nand array technology. f006h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 te c h technology information technology register setting nand slc 0000h nand mlc 0001h reserved 0002h ~ ffffh 2.8.8 technology register f006h (r)
onenand256(kfg5616x1a-xxb6) flash memory 35 2.8.10 start address2 register f101h (r/w) this register is reserved for future use. 2.8.9 start address1 register f100h (r/w) start address1 information register information description fba nand flash block address this read/write register describes the nand flash bloc k address which will be loaded, programmed, or erased. f100h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000) fba device number of block fba 256mb 512 fba[8:0]
onenand256(kfg5616x1a-xxb6) flash memory 36 2.8.12 start address4 register f103h (r/w) 2.8.11 start address3 register f102h (r/w) this read/write register describes t he nand flash destination block addres s which will be copy back programmed. f102h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000) fcba device number of block fba 256mb 512 fcba[8:0] start address3 information register information description fcba nand flash copy back block address this read/write register describes the nand flash destination page address in a bl ock and the nand flash destination sector address in a page for copy back programming. f103h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) fcpa reserved fcsa start address4 information item description default value range fcpa nand flash copy back page address 000000 000000 ~ 111111, 6 bits for 64 pages fcsa nand flash copy back sector address 0 0 ~ 1, 1 bit for 2 sectors
onenand256(kfg5616x1a-xxb6) flash memory 37 this register is reserved for future use. 2.8.14 start address6 register f105h this register is reserved for future use. 2.8.15 start addr ess7 register f106h this register is reserved for future use. 2.8.16 start address8 register f107h (r/w) 2.8.13 start address5 register f104h this read/write register describes the na nd flash start page address in a block for a page load, copy back program, or program operation and the nand flash start sector address in a pa ge for a load, copy back program, or program operation. f107h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved (00000000) fpa reserved fsa start address8 information item description default value range fpa nand flash page address 000000 000000 ~ 111111, 6 bits for 64 pages fsa nand flash sector address 0 0 ~ 1, 1 bit for 2 sectors
onenand256(kfg5616x1a-xxb6) flash memory 38 2.8.17 start buffer register f200h (r/w) this read/write register describes the bufferram sector count (bsc) and bufferram sector address (bsa). the bufferram sector count (bsc) field specifies the number of sectors to be loaded, programmed, or copy back programmed. at 0 value (the default value), the number of sector is "2". for example, if bsa = 1000, bsc = 0, then the selected bufferram will c ount up from '1000 1001'. the bufferram sector address (bsa) is the sector 0~1 addres s in the internal bootram and dataram where data is placed. f200h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) bsa reserved(0000000) bsc start buffer register information item description bsa[3] selection bit between bootram and dataram bsa[2] selection bit between dataram0 and dataram1 bsa[0] selection bit between sector0 and sector1 in the internal bootram selection bit between sector0 and sector1 in the internal dataram bsc number of sectors 11 sector 0 2 sectors bootram 0 bootram 1 bootram dataram 1_0 dataram 1_1 dataram1 { main area data spare area data dataram 0_0 dataram 0_1 dataram0 sector: (512 + 16) byte { (512b) (16b) bsa 0000 0001 1000 1001 1100 1101
onenand256(kfg5616x1a-xxb6) flash memory 39 this read/write register describes t he operation of the onenand interface. note that all command should be issued when int is turned to busy from ready state, by writing 0 to int register. after any com mand is issued, int goes back to ready state as the corresponding operation is completed. (00f0h and 00f3h may be issued during bus y at certain cases. refer to command register table below) f220h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 command note : 1) 0080h programs both main and spare area, while 001ah programs only spare area. refer to chapter 5.8 for nop limits in issuin g these commands. when using 0080h and 001ah command, read-only part in spar e area must be masked by ff. (refer to chapter 2.7.2) 2)?reset onenand?(=hot reset) command makes the registers and na nd flash core into default state as the warm reset(=reset by rp pin). cmd operation acceptable command during busy 0000h load single/multiple sector data unit into buffer 00f0h, 00f3h 0013h load single/multiple spare sector into buffer 00f0h, 00f3h 0080h program single/multiple sector data unit from buffer 1) 00f0h, 00f3h 001ah program single/multiple spare data unit from buffer 00f0h, 00f3h 001bh copy back program operation 00f0h, 00f3h 0023h unlock nand array a block - 002ah lock nand array a block - 002ch lock-tight nand array a block - 0071h erase verify read 00f0h, 00f3h 0094h block erase 00f0h, 00f3h 0095h multi-block erase 00f0h, 00f3h 00b0h erase suspend - 0030h erase resume 00f0h, 00f3h 00f0h reset nand flash core - 00f3h reset onenand 2) - 0065h otp access 00f0h, 00f3h 2.8.18 command register f220h (r/w)
onenand256(kfg5616x1a-xxb6) flash memory 40 this read/write register descri bes the system configuration. f221h, default = 40c0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r r rm brl bl ecc rdy pol int pol iobe rdy conf reserved(000) bwps read mode (rm) rm read mode 0 asynchronous read(default) 1 synchronous read read mode information[15] item definition description rm read mode selects between asynchronous read mode and synchronous read mode burst read latency (brl) brl latency cycles 000 8(n/a) 001 9(n/a) 010 10(n/a) 011 3(up to 40mhz) 100 4(default, min.) 101 5 110 6 111 7 burst read latency (brl) information[14:12] item definition description brl burst read latency specifies the access latency in the burst read transfer for the initial access 2.8.19 system configurati on 1 register f221h (r, r/w)
onenand256(kfg5616x1a-xxb6) flash memory 41 burst length (bl) bl burst length(main) burst length(spare) 000 continuous(default) 001 4 words 010 8 words 011 16 words 100 32 words n/a 101~111 reserved burst length (bl) information[11:9] item definition description bl burst length specifies the size of the burst length during a synchronous read, wrap around and linear burst read error correction code (ecc) information[8] item definition description ecc error correction code operation 0 = with correction (default) 1 = without correction (bypassed) rdy polarity (rdypol) information[7] item definition description rdypol rdy signal polarity 1 = high for ready (default) 0 = low for ready int polarity (intpol) information[6] intpol int bit of interrupt status register int pin output 0 0 (busy) high 1 (ready) low 1 (default) 0 (busy) low 1 (ready) high
onenand256(kfg5616x1a-xxb6) flash memory 42 i/o buffer enable (iobe) iobe is the i/o buffer enable for the in t and rdy signals. at startup, int and rdy outputs are high-z. bits 6 and 7 become vali d after iobe is set to "1". iobe can be reset by a cold reset or by writing "0" to bit 5 of system configuration1 register. i/o buffer enable information[5] item definition description iobe i/o buffer enable for int and rdy signals 0 = disable (default) 1 = enable boot buffer write protect status (bwps) boot buffer write protect status information[0] item definition description bwps boot buffer write protect status 0 = locked (fixed) rdy configuration (rdy conf) rdy configuration information[4] item definition description rdy conf rdy configuration 0=active one clock before valid data(default) 1=active with valid data active
onenand256(kfg5616x1a-xxb6) flash memory 43 this register is reserved for future use. 2.8.21 controller status register f240h (r) this read register shows the overall internal status of the onenand and the controller. f240h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ongo lock load prog erase error sus reserv ed(0) rstb otp l reserved(000000) to (0) ongo this bit shows the overall inter nal status of the onenand device. ongo information[15] item definition description ongo internal device status 0 = ready 1 = busy lock this bit shows whether the host is loading data from the nand flash array into t he locked bootram or whether the host is perfor m- ing a program/erase of a locked block of the nand flash array. lock information[14] lock locked/unlocked check result 0unlocked 1locked load this bit shows the load operation status. load information[13] item definition description load load operation status 0 = ready (default) 1 = busy or error (see controller status output modes) 2.8.20 system config uration 2 register f222h
onenand256(kfg5616x1a-xxb6) flash memory 44 program this bit shows the program operation status. program information[12] item definition description prog program operation status 0 = ready (default) 1 = busy or error (see controller status output modes) erase this bit shows the erase operation status. erase information[11] item definition description erase erase operation status 0 = ready (default) 1 = busy or error (see controller status output modes) error this bit shows the overall erro r status, including load reset, program reset, and erase reset status. error information[10] error current sector/page load/program/copyback. program/ erase result and invalid command input 0pass 1fail erase suspend (sus) this bit shows the erase suspend status. sus information[9] sus erase suspend status 0 erase resume(default) 1 erase suspend, program ongoing(susp.), load ongoing(susp.), program fail(susp.), load fail(susp.), invalid command(susp.)
onenand256(kfg5616x1a-xxb6) flash memory 45 reset / busy (rstb) this bit shows the reset operation status. rstb information[7] item definition description rstb reset operation status 0 = ready (default) 1 = busy (see controller status output modes) otp lock status (otp l ) this bit shows whether the otp block is lo cked or unlocked. locking the otp has the effect of a 'write-protect' to guard agains t accidental re-programming of data stored in the otp block. the otp l status bit is automatically updated at power-on. otp lock information[6] otp l otp locked/unlocked status 0 otp block unlock status(default) 1 otp block lock status(disable otp program/erase) time out (to) this bit determines if there is a time out for load, program, copy back program, and erase operati ons. it is fixed at 'no time out'. to information[0] item definition description to time out 0 = no time out
onenand256(kfg5616x1a-xxb6) flash memory 46 controller status register output modes note : 1. erm and/or ers bits in ecc status register at load fail case is 10. (2bits error - uncorrectable) 2. erm and ers bits in ecc status register at load reset case are 00. (no error) 3. multi block erase status should be checked by erase verify read operation. mode controller status register [15:0] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5:1] [0] ongo lock load prog erase error sus reserved(0) rstb otp l reserved(0) to load ongoing 1 0 1 0 0 0 0 0 0 0/1 00000 0 program ongoing 1 0 0 1 0 0 0 0 0 0/1 00000 0 erase ongoing 1 0 0 0 1 0 0 0 0 0/1 00000 0 reset ongoing 1 0 0 0 0 0 0 0 1 0/1 00000 0 multi-block erase ongoing 1 0 0 0 1 0 0 0 0 0/1 00000 0 erase verify read ongoing 1 0 0 0 0 0 0 0 0 0/1 00000 0 load ok 0 0 0 0 0 0 0 0 0 0/1 00000 0 program ok 0 0 0 0 0 0 0 0 0 0/1 00000 0 erase ok 0 0 0 0 0 0 0 0 0 0/1 00000 0 erase verify read ok 3) 0 0 0 0 0 0 0 0 0 0/1 00000 0 load fail 1) 0 0 1 0 0 1 0 0 0 0/1 00000 0 program fail 0 0 0 1 0 1 0 0 0 0/1 00000 0 erase fail 0 0 0 0 1 1 0 0 0 0/1 00000 0 erase verify read fail 3) 0 0 0 0 1 1 0 0 0 0/1 00000 0 load reset 2) 0 0 1 0 0 1 0 0 1 0/1 00000 0 program reset 0 0 0 1 0 1 0 0 1 0/1 00000 0 erase reset 0 0 0 0 1 1 0 0 1 0/1 00000 0 erase suspend 0 0 0 0 1 0 1 0 0 0/1 00000 0 program lock 0 1 0 1 0 1 0 0 0 0/1 00000 0 erase lock 0 1 0 0 1 1 0 0 0 0/1 00000 0 load lock(buffer lock) 0 1 1 0 0 1 0 0 0 0/1 00000 0 otp program fail(lock) 0 1 0 1 0 1 0 0 0 1 00000 0 otp program fail 0 0 0 1 0 1 0 0 0 0 00000 0 otp erase fail 0 1 0 0 1 1 0 0 0 0/1 00000 0 program ongo- ing(susp.) 1 0 0 1 1 0 1 0 0 0/1 00000 0 load ongoing(susp.) 1 0 1 0 1 0 1 0 0 0/1 00000 0 program fail(susp.) 0 0 0 1 1 1 1 0 0 0/1 00000 0 load fail(susp.) 0 0 1 0 1 1 1 0 0 0/1 00000 0 invalid command 0 0 0 0 0 1 0 0 0 0/1 00000 0 invalid com- mand(susp.) 0 0 0 0 1 1 1 0 0 0/1 00000 0
onenand256(kfg5616x1a-xxb6) flash memory 47 2.8.22 interrupt status register f241h (r/w) this read/write register shows st atus of the onenand interrupts. f241h, defaults = 8080h after cold reset; 8010h after warm/hot reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 int reserved(0000000) ri wi ei rsti reserved(0000) interrupt (int) this is the master interrupt bit. the int bi t is wired directly to the int pin on the chip. upon writing '0' to the int bit, th e int pin goes low if intpol is high and goes high if intpol is low. int interrupt [15] status conditions default state valid state interrupt function cold warm/hot 11 0 off sets itself to ?1? one or more of ri, wi, rsti and ei is set to ?1?, or 0065h, 0023h, 0071h, 002a and 002c com- mands are completed 0 1 pending clears to ?0? ?0? is written to this bit, or cold/warm/hot reset is being performed 1 0 off read interrupt (ri) this is the read interrupt bit. ri interrupt [7] status conditions default state valid state interrupt function cold warm/hot 10 0 off sets itself to ?1? at the completion of an load operation (0000h, 0013h, load data into buffer, or boot is done) 0 1 pending clears to ?0? ?0? is written to this bit, or cold/warm/hot reset is being performed 1 0 off write interrupt (wi) this is the write interrupt bit. wi interrupt [6] status conditions default state valid state interrupt function cold warm/hot 00 0 off sets itself to ?1? at the completion of an program operation (0080h, 001ah, 001bh) 0 1 pending clears to ?0? ?0? is written to this bit, or cold/warm/hot reset is being performed 1 0 off
onenand256(kfg5616x1a-xxb6) flash memory 48 2.8.23 start block addr ess register f24ch (r/w) this read/write register shows the nand flash block address in the write protection mode. setting this register precedes a 'loc k block' command, 'unlock block' command, or ?lock-tight' command. f24ch, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) sba device number of block sba 256mb 512 [8:0] sba information[9:0] item definition description sba start block address precedes lock blo ck, unlock block, or lock-tight commands erase interrupt (ei) this is the erase interrupt bit. ei interrupt [5] status conditions default state valid state interrupt function cold warm/hot 00 0 off sets itself to ?1? at the completion of an erase operation (0094h, 0095h, 0030h) 0 1 pending clears to ?0? ?0? is written to this bit, or cold/warm/hot reset is being performed 1 0 off reset interrupt (rsti) this is the reset interrupt bit. rsti interrupt [4] status conditions default state valid state interrupt function cold warm/hot 01 0 off sets itself to ?1? at the completion of an reset operation (00b0h, 00f0h, 00f3h or warm reset is released) 0 1 pending clears to ?0? ?0? is written to this bit 1 0 off
onenand256(kfg5616x1a-xxb6) flash memory 49 2.8.25 nand flash write protec tion status register f24eh (r) this read register shows the write protection status of the nand flash memory array. to read the write protection status, f ba has to be set before reading the register . f24eh, default = 0002h write protection status information[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000000) us ls lts item bit definition description us 2 unlocked status 1 = current nand flash block is unlocked ls 1 locked status 1 = current nand flash block is locked lts 0 locked-tight status 1 = current nand flash block is locked-tight this register is reserved for future use. 2.8.26 ecc status register ff00h (r) 2.8.24 end block addr ess register f24dh this read register shows the error correction status. the onenand can detect 1- or 2-bit errors and correct 1-bit errors. 3-bit or more error detection and correction is not supported. ecc can be performed on the nand flash main and spare memory ar eas. the ecc status register can also show the number of errors in a sector as a result of an ecc check in during a load operation. ecc status bits are also updated during a boot loadi ng oper- ation. ff00h, default = 0000h error status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) erm1 ers1 erm0 ers0 erm, ers ecc status 00 no error 01 1-bit error(correctable) 10 2 bits error (uncorrectable) 11 reserved
onenand256(kfg5616x1a-xxb6) flash memory 50 2.8.28 ecc result of 1 st selected sector, spare area data register ff02h (r) this read register shows the error correction result for the 1st selected sector of the spare area data. ecclogsector0 is the e rror position address for 1.5 words of 2nd and 3rd words in the spare area. eccposio0 is the error position address which selects 1 of 16 dqs. ecclogsector0 and eccposio0 are also updated at boot loading. ff02h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector0 eccposio0 this read register shows the error correction result for the 1st selected sector of the main area data. eccposword0 is the erro r position address in the main area data of 256 words. eccposio 0 is the error position address which selects 1 of 16 dqs. eccposword0 and eccposio0 are also updated at boot loading. ff01h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword0 eccposio0 2.8.27 ecc result of 1 st selected sector, main area data register ff01h (r) ecc information[7:0] item definition description erm0 1st selected sector of the main bufferram status of errors in the 1st selected sector of the main bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. erm1 2nd selected sector of the main bufferram status of errors in the 2nd selected sector of the main bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. ers0 1st selected sector of the spare bufferram status of errors in the 1st selected sector of the spare bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. ers1 2nd selected sector of the spare bufferram status of errors in the 2nd selected sector of the spare bufferram as a result of an ecc check during a load operation. also updated during a bootload operation.
onenand256(kfg5616x1a-xxb6) flash memory 51 this read register shows the error correction result for the 2nd selected sector of the main area data. eccposword1 is the erro r position address in the main area data of 256 words. eccposio 1 is the error position address which selects 1 of 16 dqs. eccposword1 and eccposio1 are also updated at boot loading. ff03h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword1 eccposio1 2.8.30 ecc result of 2 nd selected sector, spare area data register ff04h (r) this read register shows the error correcti on result for the 2nd selected sector of the spare area data. ecclogsector1 is the e rror position address for 1.5 words of 2nd and 3rd words in the spare ar ea. eccposio1 is the error position address which selects 1 of 16 dqs. ecclogsector1 and eccposio1 are also updated at boot loading. ff04h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector1 eccposio1 2.8.29 ecc result of 2 nd selected sector, main area data register ff03h (r) ecc log sector ecclogsector0~ecclogsector1 indicates t he error position in the 2nd word and lsb of 3rd word in the spare area. refer to note 2 in chapter 2.7.2 ecclogsector information [5:4] ecclogsector error position 00 2nd word 01 3rd word 10, 11 reserved
onenand256(kfg5616x1a-xxb6) flash memory 52 this section of the datasheet discusses the operati on of the onenand device. it is followed by ac/dc characteristics and timing diagrams which ma y be consulted for further information. the onenand supports a limited command-based interface in addition to a register-based interface for performing operations on t he device. 3.1 command based operation the command-based interface is active in the boot partition. co mmands can only be written with a boot area address. boot area d ata is only returned if no command has been issued prior to the read. the entire address range, except for the boot area, can be used for the data buffer. all commands are written to the boot parti tion. writes outside the boot partition are treated as normal writes to the buffers or registers. the command consists of one or more cycles depending on the comm and. after completion of the command the device starts its exe- cution. writing incorrect information including address and dat a to the boot partition or writing an improper command will term inate the previous command sequence and make the device enter the ready status. the defined valid command sequences are stated in command sequences table. command sequences note: 1) dp(data partition) : dataram area 2) bp(boot partition) : bootram area [0000h ~ 01ffh, 8000h ~ 800fh]. 3) load data into buffer operation is available within a block(64kb) 4) load 1kb unit into dataram0. current start address(fpa) is automatically incremented by 1kb unit after the load. 5) 0000h -> data is manufacturer id 0001h -> data is device id 0002h -> current block write protection status 6) we toggling can terminate ?read identification data? operation. command definition cycles 1st cycle 2nd cycle read data from buffer add 1 dp 1) data data write data to buffer add 1 dp data data reset onenand add 1 bp 2) data 00f0h load data into buffer 3) add 2 bp bp data 00e0h 0000h 4) read identification data 6) add 2 bp xxxxh 5) data 0090h data 3.0 device operation
onenand256(kfg5616x1a-xxb6) flash memory 53 the buffer memory can be read by addressing a read to the desired buffer area. 3.1.2 writing data to buffer the buffer memory can be written to by addressing a write to a desired buffer area. 3.1.3 reset onenand command the reset command is given by writing 00f0h to the boot partiti on address. reset will return all default values into the device . 3.1.4 load data into buffer command load data into buffer command is a two-cycle command. two s equential designated command activates this operation. sequentially writing 00e0h and 0000h to the boot partition [0000h~01ffh, 8000h~800f h] will load one page to dataram0. this operation refers to fba and fpa. fsa, bsa, and bsc are not considered. at the end of this operation, fpa will be automatically increased by 1. so continuous issue of this command will sequentially l oad data in next page to dataram0. this page address increment is restricted within a block. the default value of fba and fpa is 0. therefore, initial issue of this command after power on will load the first page of memo ry, which is usually boot code. 3.1.5 read identi fication data command the read identification data command consists of two cycles. it gives out the devices identificat ion data according to the give n address. the first cycle is 0090h to the boot partition address and second cycle is read from the addresses specified in identi fication data description table. 3.1.1 reading data from buffer identification data description note 1) to read the write protection status, fba has to be set before issuing this command. address data out 0000h manufacturer id : 00ech 0001h device id : refer to chapter 2.8.3 0002h current block write protection status 1)
onenand256(kfg5616x1a-xxb6) flash memory 54 the device bus operations are shown in the table below. note : l=v il (low), h=v ih (high), x=don?t care. operation ce oe we adq0~15 rp clk avd standby h x x high-z h x x warm reset xxxhigh-zlxx asynchronous write l h l add. in / data in hl asynchronous read l l h add. in / data out hl load initial burst read l h h add. in h burst read l l h burst data out h terminate burst read cycle h x h high-z h x x terminate burst read cycle via rp xxxhigh-zlxx terminate current burst read cycle and start new burst read cycle h h add in h h 3.2 device bus operation
onenand256(kfg5616x1a-xxb6) flash memory 55 the one nand has 4 reset modes: cold/warm/hot reset, and nand flash core reset. section 3.3 discusses the operation of these reset modes. the register reset table shows the which registers ar e affected by the various types or reset operations. internal register reset table note: 1) rdypol, intpol, iobe are reset by cold reset. the other bits except otp l are reset by cold/warm/hot reset. otp l is updated by cold reset, referring to the specified otp area. 2) ecc status register & ecc result registers are reset when any command is issued. 3) refer to device id register f001h. internal registers default cold reset warm reset (rp ) hot reset (00f3h) hot reset (bp-f0) nand flash core reset (00f0h) f000h manufacturer id register (r) 00ech n/a n/a n/a n/a f001h device id register (r): onenand (note 3) n/a n/a n/a n/a f002h version id register (r): n/a n/a n/a n/a n/a n/a f003h data buffer size register (r) 0400h n/a n/a n/a n/a f004h boot buffer size register (r) 0200h n/a n/a n/a n/a f005h amount of buffers register (r) 0201h n/a n/a n/a n/a f006h technology register (r) 0000h n/a n/a n/a n/a f100h start address1 register (r/w): fba 0000h 0000h 0000h 0000h n/a f101h start address2 register (r/w): reserved 0000h 0000h 0000h 0000h n/a f102h start address3 register (r/w): fcba 0000h 0000h 0000h 0000h n/a f103h start address4 register (r/w): fcpa, fcsa 0000h 0000h 0000h 0000h n/a f107h start address8 register (r/w): fpa, fsa 0000h 0000h 0000h 0000h n/a f200h start buffer register (r/w): bsa, bsc 0000h 0000h 0000h 0000h n/a f220h command register (r/w) 0000h 0000h 0000h 0000h n/a f221h system configuration 1 register (r/w) 40c0h 40c0h (note1) (note1) n/a f240h controller status register (r) 0000h 0000h 0000h 0000h n/a f241h interrupt status register (r/w) - 8080h 8010h 8010h n/a f24ch start block address (r/w) 0000h 0000h 0000h n/a n/a f24dh end block address: n/a n/a n/a n/a n/a n/a f24eh nand flash write protection status (r) 0002h 0002h 0002h n/a n/a ff00h ecc status register (r) (note2) 0000h 0000h 0000h 0000h 0000h ff01h ecc result of sector 0 main area data register(r) 0000h 0000h 0000h 0000h 0000h ff02h ecc result of sector 0 spare area data register (r) 0000h 0000h 0000h 0000h 0000h ff03h ecc result of sector 1 main area data register(r) 0000h 0000h 0000h 0000h 0000h ff04h ecc result of sector 1 spare area data register (r) 0000h 0000h 0000h 0000h 0000h 3.3 reset mode operation
onenand256(kfg5616x1a-xxb6) flash memory 56 at system power-up, the voltage detector in the device detects the rising edge of vcc and releases an internal power-up reset s ignal. this triggers bootcode loading. bootcode loading means that t he boot loader in the device copi es designated sized data (1kb) fr om the beginning of memory into the bootram. this sequence is the cold reset of onenand. the por(power on reset) triggering le vel is typically 1.5v. boot code copy operation activates 400us after por. therefore, the system power should reach 1.7v within 400us from the por triggering level for bootcode data to be valid. for 2.65v and 3.3v device, por level is typically 1. 8v and system power should reach 2.2v within 400us. it takes approximately 70us to copy 1kb of bootcode. upon completi on of loading into the bootram, it is available to be read by the host. the int pin is not available until afte r iobe = 1 and iobe bit can be changed by host. 3.3.2 warm r eset mode operation see timing diagrams 6.10 a warm reset means that the host resets the device by using the rp pin. when the a rp low is issued, the device logic stops all cur- rent operations and executes internal reset operation and rese ts current nand flash core operation synchronized with the falling edge of rp . during an internal reset operation, the device initializes internal registers and makes output signals go to default status. the bufferram data is kept unchanged after warm/hot reset operations. the device guarantees the logi c reset operation in case rp pulse is longer than trp min. (200ns). the device may reset if trp < trp min(200ns), but this is not guaranteed. warm reset will abort the current nand flash core operation. duri ng a warm reset, the content of memory cells being altered is no longer valid as the data will be partially programmed or erased. warm reset has no effect on contents of bootram and dataram. 3.3.3 hot re set mode operation see timing diagram 6.11 a hot reset means that the host resets the device by reset command. the reset command can be either command based or register based. upon receiving the reset command, the device lo gic stops all current operation and executes an internal reset operation and resets the current nand flash core operation. during an internal reset operation, the device initializes inte rnal registers and makes output signals go to default status. th e bufferram data is kept unchanged after warm/hot reset operations. hot reset will abort the current nand flash core operation. during a hot reset, the content of memory cells being altered is no longer valid as the data will be partially programmed or erased. hot reset has no effect on contents of bootram and dataram. 3.3.4 nand flash co re reset mode operation see timing diagram 6.12 the host can reset the nand flash core operation by issuing a na nd flash core reset command. nand flash core reset will abort the current nand flash core operation. during a nand flash core reset, the content of memory cells being altered is no lo nger valid as the data will be partially programmed or erased. hot reset has no effect on contents of bootram and dataram, as well as register values. 3.3.1 cold reset mode operation see timing diagram 6.9
onenand256(kfg5616x1a-xxb6) flash memory 57 the onenand can be write-protected to pr event re-programming or erasure of data. the areas of write-protection are the bootram, and the nand flash array. 3.4.1 bootram write protection operation at system power-up, voltage detector in the device detects the ri sing edge of vcc and releases the internal power-up reset sign al which triggers bootcode loading. and the designated size data(1kb) is copied from the first page of the first block in the nand flash array to the bootram. after the bootcode loading is completed, t he bootram is always locked to protect the boot code from the accidental write. 3.4.2 nand flash array wr ite protection operation the device has both hardware and software writ e protection of the nand flash array. hardware write protection operation the hardware write protection operation is implemented by executing a cold or warm reset. on power up, the nand flash array is in its default, locked state. the entire nand flash array goes to a locked state after a cold or warm reset. software write protection operation the software write protection operation is implemented by wr iting a lock command (002ah) or a lock-tight command (002ch) to command register (f220h). lock (002ah) and lock-tight (002ch) commands write protects t he block defined in the start block address register f24ch. 3.4.3 nand array write protection stat es there are three lock states in the nand array: unlocked, locked, and locked-tight. onenand supports lock/unlock/lock-tight by one block , so each block should be locked/ unlocked/locked-ti ght individually. write protection status the current block write protection status c an be read in nand flash write protection status register(f24eh). there are three bi ts - us, ls, lts -, which are not cleared by hot reset. these writ e protection status registers are updated when fba is set, and whe n write protection command is entered. the followings summarize locking status. example) in default, [2:0] values are 010. -> if host executes unlock bl ock operation, then [2:0] values turn to 100. -> if host executes lock-tight block operation, then [2:0] values turn to 001. 3.4 write protection operation
onenand256(kfg5616x1a-xxb6) flash memory 58 an unlocked block can be programmed or erased. the status of an unlocked block can be changed to locked or locked-tight using the appropriate software command. (locked-tight state can be achieved via lock-tight command which follows lock command) only one block can be released from lock state to unlock state with unlock command and addresses. the unlocked block can be changed with new lock command. therefore, each bl ock has its own lock/unlock/lock-tight state. unlock command sequence: start block address+unlock block command (0023h) unlocked 3.4.3.2 locked nand array writ e protection state a locked block cannot be programmed or eras ed. all blocks default to a locked state fo llowing a cold or warm reset. unlocked blocks can be changed to locked using the lock block command. the status of a lo cked block can be changed to unlocked or locked-tight using the appropriate software command. lock command sequence: start block address+lock block command (002ah) locked 3.4.3.1 unlocked nand array write protection state
onenand256(kfg5616x1a-xxb6) flash memory 59 a block that is in a locked-tight state can only be changed to lock state after a cold or warm reset. unlock and lock command sequences will not affect its state. this is an added level of write protection security. a block must first be set to a locked state before it can be changed to locked-tight using the lock-tight command. locked-tight blocks will revert to a locked state following a cold or warm reset. lock-tight command sequence: start block address+lock-tight block command (002ch) locked-tight 3.4.4 nand flash arra y write protection state diagram power on start block address +unlock block command rp pin: high & lock block command rp pin: high & +lock-tight block command rp pin: high & cold reset or unlock lock lock-tight lock lock warm reset start block address lock lock start block address cold reset or warm reset or 3.4.3.3 locked-tight nand array write protection state
onenand256(kfg5616x1a-xxb6) flash memory 60 data protection operation flow diagram start write ?sba? of flash add: f24ch dq=sba lock/unlock/lock-tight write ?lock/unlock/lock-tight? add: f220h dq=002ah/0023h/002ch wait for int register low to high transition add: f241h dq[15]=int write 0 to interrupt register add: f241h dq=0000h command completed note) samsung strongly recommend to follow the above flow chart
onenand256(kfg5616x1a-xxb6) flash memory 61 the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage detector dis ables all functions whenever vc c is below por level, about 1.3v. it is recommended that the rp pin, which provides hardware protection, s hould be kept at vil before power-down. 3.6 load operation the load operation is initiated by setting up the start address from which the data is to be loaded. the load command is issued in order to initiate the load. during a load operation, the device: -transfers t he data from nand flash array into the bufferram -ecc is checked and any detect ed and corrected error is reported in the status response as well as any unrecoverable error. once the bufferram has been filled, an interrupt is issued to the host so that the contents of the bufferram can be read. the r ead from the bufferram can be an asynchronous read mode or synchr onous read mode. the status information related to load operation can be checked by the host if required. the device has a dual data buffer memory architecture (dataram 0, dataram1), each 1kb in size. each dataram buffer has 2 sectors. the device is capable of independent and simultaneous dat a-read operation from one data buffer and data-load operation to the other data buffer. refer to the information for more details in section 3.12.1, "read-while-load operation". load operation flow chart diagram start write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc write ?load? command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int read controller add: f240h dq[10]=error dq[10]=0? no yes status register host reads data from dataram read completed map out write 0 to interrupt register add: f241h dq=0000h 3.5 data protection during power down operation see timing diagram 6.13
onenand256(kfg5616x1a-xxb6) flash memory 62 the device has two read modes; asynch ronous read and synchronous burst read. the initial state machine automatically sets the device into the asynchronous read mode (rm=0) to prevent the spurious altering of memory content upon device power up or after a hardware reset. no commands are required to retrieve data in asynchronous read mode. the synchronous read mode is enabled by setting rm bit of system configuration1 register (f221h) to synchronous read mode (rm=1). see section 2.8.19 for mo re information about system configuration1 register. 3.7.1 asynchronous read mode operation (rm=0) see timing diagrams 6.3 and 6.4 in an asynchronous read mode, data is output with respect to a logic input, avd . output data will appear on dq15-dq0 in when a valid address is asserted on a15-a0 while driving avd and ce to vil. / we is held at vih. the function of the avd signal is to latch the valid address. address access time from avd low (taa) is equal to the delay from valid addresses to valid output data. the chip enable access time (tce) is equal to the delay from the falling edge of ce to valid data at the outputs. the output enable access time (toe) is the delay from the falling edge of oe to valid data at the output. 3.7.2 synchronous re ad mode operation (rm=1) see timing diagrams 6.1 and 6.2 in a synchronous read mode, data is out put with respect to a clock input. the device is capable of a c ontinuous linear burst operation and a fixed-length linear burst operation of a preset length. bur st address sequences for continuous and fixed-length bur st operations are shown in the table below. burst address sequences in the burst mode, the initial word will be output asynchronous ly, regardless of brl. while th e following words will be determi ned by brl value. the latency is determined by the host based on the brl bit setting in the system configuration 1 register. the default brl is 4 latency cycles. at clock frequencie s of 40mhz or lower, latency cycles can be r educed to 3. brl can be set up to 7 latency cycl es. start addr. burst address sequence(decimal) continuous burst 4-word burst 8-word burst 16-word burst 32-word burst wrap around 0 0-1-2-3-4-5-6... 0-1-2-3-0... 0-1-2-3-4-5-6-7-0... 0-1-2-3-4-....-13-14-15-0... 0-1-2-3-4-....-29-30-31-0... 1 1-2-3-4-5-6-7... 1-2-3-0-1... 1-2-3-4-5-6-7-0-1... 1-2-3-4-5-....-14-15-0-1... 1-2-3-4-5-....-30-31-0-1... 2 2-3-4-5-6-7-8... 2-3-0-1-2... 2-3-4-5-6-7-0-1-2... 2-3-4-5-6-....-15-0-1-2... 2-3-4-5-6-....-31-0-1-2... . . . . . . . . . . . . 3.7 read operation see timing diagrams 6.1, 6.2, 6.3 and 6.4
onenand256(kfg5616x1a-xxb6) flash memory 63 first clock cycle the initial word is output at tiaa after the rising edge of the fi rst clk cycle. the rdy output indicates the initial word is r eady to the system by pulsing high. if the device is acce ssed synchronously while it is set to as ynchronous read mode, the first data can s till be read out. subsequent clock cycles subsequent words are output (burst access ti me from valid clock to output) tba afte r the rising edge of each successive clock cycle, which automatically increment s the internal address counter. terminating burst read the device will continue to output sequential burst data until the system asserts ce high, or rp low, wrapping around until it reaches the designated address (see section 2.7.3 for address map inform ation). alternately, a cold/warm/hot reset, asserting ce high, or a we low pulse will terminate the burst read operation. synchronous read boundary * reserved area is not available on synchronous read 3.7.2.2 4-, 8-, 16- , 32-word linear burst read operation see timing diagram 6.1 an alternate burst read mode enables a fixed number of words to be read from consecutive address. the device supports a burst read from c onsecutive addresses of 4-, 8-, 16-, and 32-words with a linear-wrap around. when the la st word in the burst has been reached, assert ce and oe high to terminate the operation. in this mode, the start address for the burst read can be any addr ess of the address map with one exception. the device does no t support a 32-word linear burst read on the spare area of the bufferram. 3.7.2.1 continuou s linear burst read operation see timing diagram 6.2 division add.map(word order) bootram main(0.5kw) 0000h~01ffh bufferram0 main(0.5kw) 0200h~03ffh bufferram1 main(0.5kw) 0400h~05ffh reserved main 0600h~7fffh bootram spare(16w) 8000h~800fh bufferram0 spare(16w) 8010h~801fh bufferram1 spare(16w) 8020h~802fh reserved spare 8030h~8fffh reserved register 9000h~efffh register(4kw) f000h~ffffh not support not support not support not support not support
onenand256(kfg5616x1a-xxb6) flash memory 64 upon power up, the number of initial clock cycles from valid address (avd ) to initial data defaults to four clocks. the number of clock cycles (n) which are inserted after the cloc k which is latching t he address. the host can read the first da ta with the (n+1)th rising edge. the number of total initial access cycles is programmable from three to seven cycles . after the number of programmed burst cloc k cycles is reached, the rising edge of the nex t clock cycle triggers the next burst data. four clock burst read latency (default condition) 3.7.3 handshaking operation the handshaking feature allows the host system to simply monitor the rdy signal from the device to determine when the initial word of burst data is ready to be read. to set the number of initial cycles for optimal burst mode, t he host should use the programmable burst read latency configurati on (see section 2.8.19, "system configuration1 register"). the rising edge of rdy which is derived at the same cycle of data fetch clock indica tes the initial word of valid burst data. 3.7.2.3 programmable burs t read latency operation see timing diagrams 6.1 and 6.2 t iaa hi-z ce clk avd oe rdy t rdys t rdya dq0: dq15 d6 d7 d0 d1 d2 d3 d7 d0 hi-z 0123 -1 t ba rising edge of the clock cycle following last read latency triggers next burst data a0: a15 valid address 4
onenand256(kfg5616x1a-xxb6) flash memory 65 when the ce or oe input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. the program operation is used to program data from the on-chip bufferrams into the nand flash memory array. the device has two 1kb data buffers, each 1 page (1kb + 32b) in size. each page has 2 sectors of 512b each main area and 16b spare area. the device can be programmed in units of 1~2 sectors. the architecture of the datarams permits a simultaneous data- write operation from the host to one of data buffers and a program operation from the other data buffer to the nand flash array memory. refer to section 3.12.2, "write while program operation", for more information. 3.8 program operation within a block, the pages must be programme d consecutively from the lsb (least significant bit) page of the block to msb (most sig- nificant bit) pages of the block. r andom page address programming is prohibited. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 addressing for program operation : : : : 3.7.4 output disable mode operation
onenand256(kfg5616x1a-xxb6) flash memory 66 program operation flow diagram during the execution of the internal program routine, t he host is not required to provide any further controls or timings. furthermore, all commands, except a reset command, wi ll be ignored. a reset during a program operation will cause dat a corruption at the corresponding location. if a program error is detected at the completion of the internal program routine, map out the block, including the page in err or, and copy the target data to another block. an error is signal ed if dq10 = "1" of controller status register(f240h) . data input from the host to the dataram can be done at any time during the internal program routine after "start" but before th e "write program command" is written. start data input write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write data into dataram 2) add: dp dq=data-in program completed write ?program? command add: f220h dq=0080h or 001ah completed? wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? program error yes no no yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * write 0 to interrupt register add: f241h dq=0000h write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc note 1) this must happen before data input 2) data input could be done anywhere between "start" and "write program command".
onenand256(kfg5616x1a-xxb6) flash memory 67 the copy-back program is configured to qu ickly rewrite data stored in one page without utilizing memory other than onenand. since the time-consuming cycles of serial access and re-loading c ycles are removed, the system performance is improved. the ben - efit is especially obvious when a portion of block is updated and the rest of the blo ck also need to be copied to the newly ass igned free block. data from the source page is saved in one of the on-chip dataram buffers and then programmed directly into the destination page . the dataram overwrites the previous data using the buffer sector a ddress (bsa) and buffer sector count (bsc). the copy-back program operation does this by performing s equential page-reads without a serial access and executing a copy-program using the address of the destination page. copy-back program operation flow chart start write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?fcba? of flash add: f102h dq=fcba write ?fcpa, fcsa? of flash add: f103h dq=fcpa, fcsa copy back completed write ?copy-back program? command add: f220h dq=001bh wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? copy back error yes no note 1) selected dataram by bsa & bsc is used for copy back operation, so previous data is overwritten. : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * 2) fba, fpa and fsa should be input prior to fcba, fcpa and fcsa. write 0 to interrupt register add: f241h dq=0000h write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc 1) 3.9 copy-back program operation
onenand256(kfg5616x1a-xxb6) flash memory 68 the copy-back steps shown in the flow chart are: ? data is read from the nand array using flash bl ock address (fba), flash page address (fpa) and flash sector address (fsa). fba, fpa, and fsa identify the source address to read data from nand flash array. ? the bufferram sector count (bsc) and bufferram se ctor address (bsa) identifies how many sectors and the location of the sectors in dataram that are used. ? the destination address in the nand array is writt en using the flash copy-ba ck block address (fcba), flash copy-back page addre ss (fcpa), and flash copy-bac k sector address (fcsa). ? the copy-back program command is issued to start programming. ? upon completion of copy-back programming to the destination page address, the host checks the status to see if the operation was successful ly completed. if there was an error, map out the block including the page in error and copy the target data to another block.
onenand256(kfg5616x1a-xxb6) flash memory 69 the copy-back program operation with random data input in onen and consists of 2 phase, load data into dataram, modify data and program into designated page. data from the source page is saved in one of the on-chip dataram buffers and modified by the host, then programmed into the destination page. as shown in the flow chart, data modificati on is possible upon completion of load operatio n. ecc is also available at the end o f load operation. therefore, using hardware ecc of onen and, accumulation of 1 bit error can be avoided. copy-back program operation with random data input will be effect ively utilized at modi fying certain bit, byte, word, or sector of source page to destination p age while it is being copied. copy-back program operation with random data input flow chart start write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc write ?load? command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int read controller add: f240h dq[10]=error dq[10]=0? no yes status register map out write 0 to interrupt register add: f241h dq=0000h copy back completed wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? copy back error yes no random data input write ?fba? of flash add: f100h dq=fba write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?program? command add: f220h dq=0080h or 001ah write 0 to interrupt register add: f241h dq=0000h add: random address in selected dataram dq=data 3.9.1 copy-back program op eration with random data input see timing diagram 6.7
onenand256(kfg5616x1a-xxb6) flash memory 70 there are multiple methods for erasing data in th e device including block erase and multi-block erase. 3.10.1 block erase operation see timing diagram 6.8 the device can be erased one block at a time. to erase a block is to write all 1's into the desired memory block by executing t he inter- nal erase routine. all previous data is lost. block erase operation flow chart start write ?fba? of flash add: f100h dq=fba write ?erase? command add: f220h dq=0094h wait for int register add: f241h dq=[15]=int add: f240h dq[10]=error erase completed dq[10]=0? yes erase error no low to high transition read controller status register : if erase operation results in an error, map out the failing block and replace it with another block. * write 0 to interrupt register add: f241h dq=0000h 3.10 erase operation
onenand256(kfg5616x1a-xxb6) flash memory 71 in order to perform the internal erase rout ine, the following comm and sequence is necessary. ? the host sets the block address of the memory location. ? the erase command initiates the internal erase routin e. during the execution of the routine, the host is not required to provide further controls or timings. during the internal erase routine, all commands, except the reset command and eras e suspend command, written to the device will be ignored. a reset during an erase operation will cause data corruption at the corresponding location. using multi-block erase, the device can eras e up to 64 multiple blocks simultaneously. multiple blocks can be erased by issuing a multi-block erase command and writing the block address of the memory location to be erased. the final flash block address (fba) and block erase command initiate the internal multi block erase routine. during a multi-block erase, the ongo bit of the cont roller status register is set to '1'(busy) from the time first block address to be l atched is written until the actual erase has finished. during block address latch sequence, issuing of other commands ex cept block erase and multi bloc k erase at int=high will abort the current operation. so to speak, it will cancel the pr eviously latched addresses of multi block erase operation. on the other hand, other command issue at int=low will be ignored. a reset during an erase operation will cause data corrupti on at the address location being operated on during the reset. despite a failed block during multi-block erase operation, the de vice will continue the erase oper ation until all other specifi ed blocks are erased. erase suspend command issue during multi bloc k erase address latch sequence is prohibited. locked blocks if there are locked blocks in the specified range, t he multi-block erase operation works as the follows. case 1: all specified blocks except ba(2) will be erased. [ba(1)+0095h] + [ ba((2), locked) +0095h] + ... + [ba(n-1)+0095h] + [ba(n)+0094h] case 2: multi-block erase operation is su spended and fails to start if the last block erase command is put together with the lo cked block address until right command and address input are issued. [ba(1)+0095h] + [ba(2)+0095h] + ... + [ba(n-1)+0095h] + [ ba((n), locked) +0094h] case 3: all specified blocks except ba(n) are erased. [ba(1)+0095h] + [ba(2)+0095h] + ... + [ba(n-1)+0095h] + [ ba((n), locked) +0094h] + [ba(n+1)+0094h] 3.10.2 multi-blo ck erase operation see timing diagram 6.8
onenand256(kfg5616x1a-xxb6) flash memory 72 after a multi-block erase operation, verify erase operation result of each block with multi-block erase verify command combined with address of each block. if a failed address is identified, it must be managed in firmware. multi block erase/ multi block erase verify read flow chart start write ?fba? of flash add: f100h dq=fba write ?multi block erase? add: f220h dq=0095h wait for int register add: f241h dq=[15]=int final multi block yes no low to high transition write 0 to interrupt register add: f241h dq=0000h command erase? write ?fba? of flash add: f100h dq=fba write ?block erase add: f220h dq=0094h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register add: f241h dq=0000h command? multi block erase verify read write ?fba? of flash add: f100h dq=fba write ?multi block erase add: f220h dq=0071h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register add: f241h dq=0000h verify read command? read controller add: f240h dq[10]=error status register dq[10]=0? multi block erase completed final multi block yes no erase address? erase completed yes erase error no 3.10.3 multi-block erase verify read operation
onenand256(kfg5616x1a-xxb6) flash memory 73 the erase suspend/erase resume commands interrupt and restart a bl ock erase or multi-block erase operation so that user may perform another urgent operation on the block that is not being designated by erase/mu lti-block erase operation. erase suspend during a block erase operation when erase suspend command is written during a block erase or mu lti-block erase operation, the device requires a maximum of 500us to suspend erase operation. erase suspend command issue during block address latch sequence is prohibited. after the erase operation has been suspended, the device is ready for the next operation including a load, program, copy-back program, lock, unlock, lock-tight, hot rese t, nand flash core reset, command based reset, multi-block erase read verify, or otp access. the subsequent operation can be to any block that was not being erased. a special case arises pertaining erase sus pend to the otp. a reset command is used to exit from the otp access mode. if the reset-triggered exit from the otp access mode happens during an erase suspend operation, the erase routine could fail. therefor e to exit from the otp access mode wit hout suspending the erase operation stop, a 'nand flash core reset' command should be issued. for the duration of the erase suspend peri od the following commands are not accepted: ? block erase/multi-blo ck erase/erase suspend erase suspend and erase resume operation flow chart start write ?erase suspend add: f220h dq=00b0h wait for int register add: f241h dq=[15]=int low to high transition for 500us command? 1) write 0 to interrupt register add: f241h dq=0000h write ?erase resume add: f220h dq=0030h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register add: f241h dq=0000h command? another operation * * another operation ; load, program copy-back program, otp access 2) , hot reset, flash reset, cmd reset, multi block erase verify, lock, lock-tight, unlock check controller status register do multi block erase verify read in case of block erase in case of multi block erase 2) if otp access mode exit happens with reset operation during erase suspend mode, reset operation could hurt the erase operation. so if a user wants to exit from otp access mode without the erase operation stop, reset nand flash core command should be used. note 1) erase suspend command input is prohibited during multi block erase address latch period. 3.10.4 erase suspend / erase resume operation
onenand256(kfg5616x1a-xxb6) flash memory 74 erase resume when the erase resume command is executed, the block erase will restart. the erase resume operation does not actually resume the erase, but starts it again from the beginning. when an erase suspend or erase resume command is executed, the addresses are in don't care state. for multi block erase, erase suspend/resume can be operated after final erase command (0094h) is issued. therefore, erase resume operation does not actually resume from the erased block. but resumes the multi block erase from the begging. on block of the nand flash array memory is rese rved as a one-time programmable block memory area. the otp block can be read, programmed and locked using the same operations as any other nand flash array memory block. otp block cannot be erased. otp block is fully-guaran teed to be a valid block. entering the otp block the otp block is separately accessible from the rest of the nand flash array by using the ot p access command instead of the flash block address (fba). exiting the otp block to exit the otp access mode, a cold-, warm-, hot- , or nand flash core reset operation is performed. exiting the otp block during an erase operation if the reset-triggered exit from the otp access mode happens during an erase suspend operation, the erase routine could fail. therefore to exit from the otp ac cess mode without suspending the erase operation stop, a 'nand flash core reset' command should be issued. the otp block page assignments otp area is one block size ((64k+2k)b, 64 pages) and is divided into two areas. the 20 -page user area is available as an otp st or- age area. the 44-page manufacturer area is programmed by the manufacturer prior to shipping the device to the user. otp block page allocation information area page use user 0 ~ 19 (20 pages) designated as user area manufacturer 20 ~ 63 (44 pages) us ed by the device manufacturer 3.11 otp operation
onenand256(kfg5616x1a-xxb6) flash memory 75 otp area structure page:1kb+32b sector(main area):512b sector(spare area):16b one block: 64kb+2kb 64pages manufacturer area : page 20~ page 63 44pages user area : page 0~ page 19 20pages
onenand256(kfg5616x1a-xxb6) flash memory 76 an otp load operation accesses the otp ar ea and transfers identified content from the otp to the dataram on-chip buffer, thus making the otp contents available to the host. the otp area is a separate part of the nand flash array memo ry. it is accessed by issuing otp access command(65h) instead of a flash block address (fba) command. after being accessed with the ot p access command, the contents of otp memory area are loaded using the same operations as a normal load operation to the nand flash array memory (see section 3.6 for more information). to exit the otp access mode following an otp load operation, a cold -, warm-, hot-, or nand flash core reset operation is perfor med. otp read operation flow chart start wait for int register add: f241h dq[15]=int write 0 to interrupt register add: f241h dq=0000h write ?fpa, fsa? of flash 1) add: f107h dq=fpa, fsa otp reading completed write ?load? command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int write ?otp access? command add: f220h dq=0065h write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc low to high transition otp exit host reads data from dataram note 1) fba(nand flash block address) could be omitted or could be any address. do cold/warm/hot /nand flash core reset write ?fba? of flash 1) add: f100h dq=fba write 0 to interrupt register add: f241h dq=0000h 3.11.1 otp load operation
onenand256(kfg5616x1a-xxb6) flash memory 77 an otp program operation accesses the otp area and program s content from the dataram on-chip buffer to the designated page(s) of the otp. a memory location in the otp area can be programmed only one time (no erase operation permitted). the otp area is programmed using the same sequence as norma l program operation after bei ng accessed by the command (see section 3.8 for more information). programming the otp area ? issue the otp access command ? write data into the dataram (data can be input at anyti me between the "start" and "write program" commands) ? issue a flash block address (fba) which is unlo cked area address of nand flash array address map. ? issue a write program command to program the data from the dataram into the otp ? when the otp programming is complete, do a cold-, warm-, ho t-, nand flash core reset to exit the otp access mode. 3.11.2 otp program operation
onenand256(kfg5616x1a-xxb6) flash memory 78 otp program operation flow chart write ?fba? of flash 1) add: f100h dq=fba start data input write ?otp access? command add: f220h dq=0065h write data into dataram 2) add: dp dq=data-in otp programming completed write program command dq=0080h or 001ah completed? wait for int register low to high transition add: f241h dq[15]=int no add: f220h wait for int register add: f241h dq[15]=int low to high transition do cold/warm/hot otp exit automatically checked update controller add: f240h status register wait for int register low to high transition add: f241h dq[15]=int otp exit automatically otp l =0? yes no updated read controller status register add: f240h dq[10]=1(error) dq[14]=1(lock), dq[10]=1(error) 2) data input could be done anywhere between "start" and "write program command". note 1) fba(nand flash block address) could be omitted or any address. read controller status register add: f240h dq[10]=0(pass) /nand flash core reset do cold/warm/hot /nand flash core reset write 0 to interrupt register add: f241h dq=0000h 3) fba should point the unlocked area address among nand flash array address map. write ?fpa, fsa? of flash add: f107h dq=fpa, fsa write ?bsa, bsc? of dataram add: f200h dq=bsa, bsc add: f200h dq=bsa, bsc write ?fba? of flash add: f100h dq=fba 3) write 0 to interrupt register add: f241h dq=0000h
onenand256(kfg5616x1a-xxb6) flash memory 79 even though the otp area can only be programmed once without eras e capability, it can be locked when the device starts up to prevent any changes from being made. unlike the main area of the nand flash array memory, once the otp block is locked, it cannot be unlocked. locking the otp programming to the otp area can be prevented by locki ng the otp area. locking the otp area is accomplished by programming xxxch to 8th word of sector0 of page0 of the spare0 memory area. at device power-up, this word location is checked and if xxxch is found, the otpl bit of the controller status register is set to "1", indicating the otp is locked. when the program operation finds that the status of t he otp is locked, the device updates the err or bit of the controller status register as "1" (fail). otp lock operation steps ? issue the otp access command ? fill data to be programmed into dataram (data can be input at anytime between the "start" and "write program" commands) ? write 'xxxch' data into the 8th word of sector0 of page0 of the spare0 memory area of the dataram. ? issue a flash block address (fba) to unlocked address in the nand flash array address map. ? issue a program command to program the data from the dataram into the otp ? when the otp lock is complete, do a cold reset to exit the otp access mode and update otp lock bit[6]. ? otp lock bit[6] of the controller status regist er will be set to "1" and the otp will be locked. 3.11.3 otp lock operation
onenand256(kfg5616x1a-xxb6) flash memory 80 otp lock operation flow chart start write ?fpa, fsa? of flash add: f107h dq=0000h write ?bsa, bsc? of dataram add: f200h dq=0001h write data into dataram 2) add: 8th word write program command dq=0080h or 001ah wait for int register low to high transition add: f241h dq[15]=int add: f220h write 0 to interrupt register add: f241h dq=0000h automatically updated dq=xxxch in spare0/sector0/page0 update controller add: f240h status register otp lock completed dq[6]=1(otp l ) write ?fba? of flash add: f100h dq=fba 3) write ?otp access? command add: f220h dq=0065h wait for int register add: f241h dq[15]=int low to high transition write 0 to interrupt register add: f241h dq=0000h do cold reset write ?fba? of flash 1) add: f100h dq=fba 2) data input could be done anywhere between "start" and "write program command". note 1) fba(nand flash block address) could be omitted or any address. 3) fba should point the unlocked area address among nand flash array address map.
onenand256(kfg5616x1a-xxb6) flash memory 81 the device has independent dual data buffe rs on-chip (except during the boot load period) that enables higher performance read and program operation. 3.12.1 read-whi le-load operation this operation accelerates the read performance of the device by enabling data to be read out by the host from one dataram buff er while the other dataram buffer is being loaded wi th data from the nand flash array memory. page a page b 1) data load 2) data load data buffer1 data buffer0 2) data read 3) data read 3) data load the dual data buffer architecture provides the capability of executing a data-read operation from one of dataram buffers during a simultaneous data-load operation from flash to the other buffe r. simultaneous load and read operation to same data buffer is prohibited. see sections 3.6 and 3.7 for mo re information on load and read operations. if host sets fba, fsa, or fpa while loading into designated page, it will fail the internal l oad operation. address registers should not be updated until internal operation is completed. 3.12.2 write-while-program operation this operation accelerates the programming performance of the dev ice by enabling data to be written by the host into one datara m buffer while the nand flash array memory is being programmed with data from the other dataram buffer. page a page b 2) program 3) program data buffer1 data buffer0 1) data write 2) data write 3) data write the dual data buffer architecture provides the capability of ex ecuting a data-write operation to one of dataram buffers during simul- taneous data-program operation to flash from the other buffer. simultaneous program and write operation to same data buffer is prohibited. see sections 3.8 for more information on program operation. if host sets fba, fsa, or fpa while programming into designated page , it will fail the internal program operation. address reg isters should not be updated until internal operation is completed. 3.12 dual operations
onenand256(kfg5616x1a-xxb6) flash memory 82 read while load diagram page b add we oe int 0~15 2) 2) page a 1) add_ reg int_ reg cmd_ reg cs_ reg data load _db0 data load _db1 data read _db0 * add_ reg int_ reg cmd_ reg add_ reg add_ reg db1 _add ld_ cmd read status db0 _add 0000h ld_ cmd flash dq 0~15 int_reg : interrupt register address add_reg : address register address flash_add : flash address to be loaded dbn_add : dataram address to be loaded cmd_reg : command register address ld_cmd : load command data load_dbn : load data from nand flash array to dataramn cs_reg : controller status register address data read_dbn : read data from dbn dbn_radd : dataram address to be read 1) data load _db0 db0_radd* data load _db1 _add 0000h flash _add * dbs should be set before accessing dataram for ddp
onenand256(kfg5616x1a-xxb6) flash memory 83 write while program diagram page b add oe int 0~15 page a 1) we db0_wadd* add_ reg add_ reg int_ reg cmd_ reg cs_ reg int_ reg cmd_ reg data pgm _pageb dq 0~15 db0 _add flash _add 0000h pd_ cmd data write _db1 * db1 _add read status 0000h pd_ cmd data pgm _pagea add_reg : address register address dbn_add : dataram address to be programmed dbn_wadd : dataram address to be written data write_dbn : write data to dataramn flash_add : flash address to be programmed int_reg : interrupt register address cmd_reg : command register address pd_cmd : program command data pgm_pagea : program data from dataram to pagea cs_reg : controller status register address data write _db0 * db1_wadd* data pgm _pagea 2) add_ reg add_ reg flash _add data write _db0 * db0_wadd* data pgm _pageb * dbs should be set before accessing dataram for ddp
onenand256(kfg5616x1a-xxb6) flash memory 84 the onenand device has on-chip ecc with the capability of detecting 2 bit errors and correcting 1-bit errors in the nand flash array memory main and spare areas. as the device transfers data from a bufferram to the nand flash array memory page buffer for pr ogram operation, the device ini- tiates a background operation which generates an error correction c ode (ecc) of 24bits for each sector main area data and 10bit s for 2nd and 3rd word data of each sector spare area. during a load operation from the nand flash array memory page, the on-chip ecc engine generates a new ecc. the 'load ecc result' is compared to the originally 'program ecc' thus detec ting the number and position of errors. single-bit error is corre cted. ecc is updated by the device automatically. after a load operatio n, the host can determine whether there was error by reading t he 'ecc status register' (refer to section 2.8.26). error types are divided into 'no erro r', '1bit correctable error', and '2bit error uncorrectable error'. onenand supports 2bit edc even though 2bit erro r seldom or never occurs. hence, it is not recommeded for host to read 'ecc sta- tus register' for checking ecc error because the built-in erro r correction logic of onenand aut omatically corrects ecc error. when the device reads the nand flash array memory main and sp are area data with an ecc operation, the device doesn't place the newly generated ecc for main and spare area into the buffer. instead it places the ecc which was generated and written duri ng the program operation into the buffer. an ecc operation is also done during the boot loading operation. 3.13.1 ecc bypass operation 3.13 ecc operation in an ecc bypass operation, the device does not generate ecc as a background operation. the result does not indicate error posi - tion (refer to the ecc result table). in a program operation the ecc code to nand flash array memory spare area is not updated. during a load operation, the on-chip ecc engine does not generate a ne w ecc internally. also the ecc status & result to regis- ters are invalid. the error is not corrected and detected by itself, so that ecc bypass operation is not recommended for host. ecc bypass operation is set by the 9bit of system configuration 1 register (see section 2.8.19) ecc code and ecc result by ecc operation note: 1. pre-written ecc code : ecc code which is previously written to nand flash spare area in program operation. operation program operation load operation ecc code update to nand flash array spare area ecc code at bufferram spare area ecc status & result update to registers 1bit error ecc operation update pre-written ecc code (1) loaded update correct ecc bypass not update pre-written code (1) loaded invalid not correct
onenand256(kfg5616x1a-xxb6) flash memory 85 invalid blocks are defined as blocks in the device's nand flash array memory that cont ain one or more invalid bits whose reliab ility is not guaranteed by samsung. the information regarding the invalid block(s) is called the invalid block information. devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the per formance of valid block(s) because it is isolated from the bit line and the common s ource line by a select transistor. the system design must be able to mask ou t the invalid block(s) via address mapping. the 1st block, which is placed on 00h bloc k address, is always fully guaranteed to be a valid block. due to invalid marking, during load operation for identifying invalid block, a load error may occur. 3.14.1 invalid block id entification table operation a system must be able to recognize invali d block(s) based on the original invalid bl ock information and create an invalid block table. invalid blocks are identified by erasing al l address locations in the nand flash array memory except locations where the invali d block(s) information is written prior to shipping. an invalid block(s) status is defined by the 1st word in the sp are area. samsung makes sure that either the 1st or 2nd page of every invalid block has non-ffffh data at the 1st word of sector0. since the invalid block informati on is also erasable in most cases, it is impos sible to recover the information once it has bee n erased. any intentional erase of the original in valid block information is prohibited. the following suggested flow chart can be used to create an invalid block table. 3.14 invalid block operation
onenand256(kfg5616x1a-xxb6) flash memory 86 invalid block table creation flow chart within its life time, additional invalid bl ocks may develop with nand flash array me mory. refer to the device's qualification r eport for the actual data. the following possible failure m odes should be considered to im plement a highly reliable system. in the case of a status read failure after erase or program, a block replacement should be done. because program status failure during a page program does not affect the data of the other pages in the same block, a block repl acement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replac ed block. block failure modes and countermeasures failure mode detection and countermeasure sequence erase failure status read after erase --> block replacement program failure status read after program --> block replacement single bit failure in load operation error correction by ecc mode of the device 3.14.2 invalid block replacement operation * start set block address = 0 check increment block address last block ? end no yes yes create (or update) no invalid block(s) table "ffffh" ? check "ffffh" at the 1st word of sector 0 of spare area in 1st and 2nd page
onenand256(kfg5616x1a-xxb6) flash memory 87 referring to the diagram for further illustration, when an error happens in the nth page of block 'a' during program operation, copy the data in the 1st ~ (n-1)th page to the same location of block 'b' via data buffer0. then copy the nth page data of block 'a' in the data buffer1 to the nth page of block 'b' or any free block. do not further era se or program block 'a' but instead complete the operation by creat ing an 'invalid block table' or other appropriate scheme. block replacement operation sequence data buffer1 of the device 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2 data buffer0 of the device 1 (assuming the nth page data is maintained)
onenand256(kfg5616x1a-xxb6) flash memory 88 4.1 absolute maximum ratings notes : 1. minimum dc voltage is -0.5v on input/ output pins. during trans itions, this level should not fall to por level(typ. 1.5v@1.8 v device, 1.8v@2.65v/ 3.3v device). maximum dc voltage is vcc+0.6v on input / output pi ns which, during transitions, ma y overshoot to vcc+2.0v for pe riods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss vcc vcc (for 1.8v) -0.5 to + 2.45 v vcc (for 2.65v/3.3v) -0.5 to + 4.6 all pins v in (for 1.8v) -0.5 to + 2.45 v in (for 2.65v/3.3v) -0.5 to + 4.6 temperature under bias extended t bias -30 to +125 c industrial -40 to +125 storage temperature t stg -65 to +150 c short circuit output current i os 5ma recommended operating temperature t a (extended temp.) -30 to +85 c t a (industrial temp.) -40 to +85 4.2 operating conditions 4.0 dc characteristics voltage reference to gnd notes : 1. the system power should reach 1.7v after por triggering level(typ. 1.5v) within 400us. for 2.65v and 3.3v device, the system power should re ach 2.2v after por triggering level(typ. 1.8v) within 400us. 2. vcc-core (or vcc) should reach the operating voltage leve l prior to or at the same time as vcc-io (or vccq). parameter symbol 1.8v device 2.65v device 3.3v device unit min typ. max min typ. max min typ. max supply voltage v cc- core / vcc 1.7 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 v v cc- io / vccq v ss 000000000v
onenand256(kfg5616x1a-xxb6) flash memory 89 4.3 dc characteristics note 1. ce should be vih for rdy. iobe should be ?0? for int. note 2. icc active for host access note 3. icc active for internal operation. (without host access) note 4. vccq is equivalent to vcc-io parameter symbol test conditions 1.8v device 2.65v device 3.3v device unit min typ max min typ max min typ max input leakage current i li v in =v ss to v cc , v cc =v ccmax - 1.0 - + 1.0 - 1.0 - + 1.0 - 1.0 - + 1.0 a output leakage current i lo v out =v ss to v cc , v cc =v ccmax , ce or oe =v ih (note 1) - 1.0 - + 1.0 - 1.0 - + 1.0 - 1.0 - + 1.0 a active asynchronous read current (note 2) i cc1 ce =v il , oe =v ih - 8 15 - 14 20 - 14 20 ma active burst read current (note 2) i cc2 ce =v il , oe =v ih 66mhz - 15 25 - 20 30 - 20 30 ma 1mhz - 3 4 - 5 7 - 5 7 ma active write current (note 2) i cc3 ce =v il , oe =v ih - 8 15 - 17 22 - 17 22 ma active load current (note 3) i cc4 ce =v il , oe =v ih , we =v ih -3040-3040-3040ma active program current (note 3) i cc5 ce =v il , oe =v ih , we =v ih -2530-2835-2835ma active erase current (note 3) i cc6 ce =v il , oe =v ih , we =v ih -2025-2330-2330ma multi block erase cur- rent (note 3) i cc7 ce =v il , oe =v ih , we =v ih , 64blocks - 20 25 - 23 30 - 23 30 ma standby current i sb ce = rp =v cc 0.2v - 10 50 - 25 80 - 25 80 a input low voltage v il - -0.5 - 0.4 -0.5 - 0.4 0 - 0.8 v input high voltage (note 4) v ih - v ccq -0.4 - v ccq +0.4 v ccq -0.4 - v ccq +0.4 0.7* v ccq -v ccq v output low voltage v ol i ol = 100 a , v cc =v ccmin , v ccq =v ccqmin --0.2--0.2-- 0.22* vccq v output high voltage v oh i oh = -100 a , v cc =v ccmin , v ccq =v ccqmin v ccq -0.1 -- v ccq -0.4 -- 0.8* v ccq --v
onenand256(kfg5616x1a-xxb6) flash memory 90 5.1 ac test conditions parameter value input pulse levels 0v to v cc input rise and fall times clk 3ns other inputs 5ns input and output timing levels v cc /2 output load c l = 30pf 0v v cc v cc /2 v cc /2 input pulse and test point input & output test point output load device under te s t * c l = 30pf including scope and jig capacitance 5.2 device capacitance notes: 1. the device may include invalid blocks when first shipped. additional inva lid blocks may develop while being used. the number of valid blo cks is pre- sented with both cases of invalid blocks considered. invalid bl ocks are defined as blocks that contain one or more bad bits . do not erase or program factory-marked bad blocks. 2. the 1st block, which is placed on 00h bloc k address, is fully guaranteed to be a valid block. parameter symbol min typ. max unit valid block number n vb 502 - 512 blocks capacitance (t a = 25 c, v cc = 1.8v, f = 1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition single unit min max input capacitance c in1 v in =0v - 10 pf control pin capacitance c in2 v in =0v -10 output capacitance c out v out =0v - 10 int capacitance c int v out =0v - 15 5.3 valid block characteristics 5.0 ac characteristics
onenand256(kfg5616x1a-xxb6) flash memory 91 5.4 ac characteristic s for synchronous burst read see timing diagrams 6.1, 6.2 note 1. if oe is disabled at the same time or before ce is disabled, the output will go to high-z by t oez . if ce is disabled at the same time or before oe is disabled, the output will go to high-z by t cez . if ce and oe are disabled at the same time, th e output will go to high-z by t oez . 2. it is the following clock of address fetch clock. parameter symbol kfg5616x1a unit min max clock clk 1 66 mhz clock cycle t clk 15 - ns initial access time t iaa -70ns burst access time valid clock to output delay t ba -11.5ns avd setup time to clk t avds 5-ns avd hold time from clk t avdh 6-ns address setup time to clk t acs 5-ns address hold time from clk t ach 6-ns data hold time from next clock cycle t bdh 4-ns output enable to data t oe -20ns ce disable to output high z t cez 1) -20ns oe disable to output high z t oez 1) -15ns ce setup time to clk t ces 6-ns clk high or low time t clkh/l t clk /3 - ns clk 2) to rdy valid t rdyo -11.5ns clk to rdy setup time t rdya -11.5ns rdy setup time to clk t rdys 3.5 - ns ce low to rdy valid t cer -15ns
onenand256(kfg5616x1a-xxb6) flash memory 92 note: 1. if oe is disabled at the same time or before ce is disabled, the output will go to high-z by toez. if ce is disabled at the same time or before oe is disabled, the output will go to high-z by tcez. if ce and oe are disabled at the same time, the output will go to high-z by toez. these parameters are not 100% tested. parameter symbol kfg5616x1a unit min max unit access time from ce low t ce -76ns asynchronous access time from avd low t aa -76ns asynchronous access time from address valid t acc -76ns read cycle time t rc 76 - ns avd low time t avdp 12 - ns address setup to rising edge of avd t aavds 7-ns address hold from rising edge of avd t aavdh 7-ns output enable to output valid t oe -20ns we disable to oe enable t oeh 0-ns ce setup to avd falling edge t ca 0-ns ce disable to output & rdy high z 1) t cez -20ns oe disable to output high z 1) t oez -15ns we disable to avd enable t wea 15 - ns note 1. these parameters are tested based on int bit of interrupt r egister. because the time on int pin is related to the pull-up an d pull-down resistor value. 2. the device may reset if trp < trp mi n(200ns), but this is not guaranteed. parameter symbol min max unit rp & reset command latch to bootram access tready1 (bufferram) -5 s rp & reset command latch(during load routines) to int high (note1) tready2 (nand flash array) -10 s rp & reset command latch(during program routines) to int high (note1) tready2 (nand flash array) -20 s rp & reset command latch(during erase routines) to int high (note1) tready2 (nand flash array) - 500 s rp & reset command latch(not during internal routines) to int high (note1) tready2 (nand flash array) -10 s rp pulse width (note2) trp 200 - ns 5.5 ac characteris tics for asynchronous read see timing diagrams 6.3, 6.4, 6.5 and 6.6 5.6 ac characteristics for warm reset (rp ), hot reset and nand flash core reset see timing diagrams 6.12, 6.13 and 6.14
onenand256(kfg5616x1a-xxb6) flash memory 93 parameter symbol min typ max unit we cycle time t wc 70 - - ns avd low pulse width t avdp 12 - - ns address setup time t awes 0 - - ns address hold time t ah 30 - - ns data setup time t ds 25 - - ns data hold time t dh 0 - - ns ce setup time t cs 0 - - ns ce hold time t ch 10 - - ns we pulse width t wpl 40 - - ns we pulse width high t wph 30 - - ns avd disable to we disable t vlwh 15 - - ns we disable to avd enable t wea 15 - - ns 5.8 ac characteristics for load/program/erase performance see timing diagrams 6.8, 6.9, and 6.10 note 1) these parameters are tested based on int bit of interrupt register. because the time on int pin is related to the pull- up and pull-down resistor value. parameter symbol min typ max unit sector load time(note 1) t rd1 -2335 s page load time(note 1) t rd2 -2540 s sector program time(note 1) t pgm1 - 205 720 s page program time(note 1) t pgm2 - 220 750 s otp access time(note 1) t otp - 500 700 ns lock/unlock/lock-tight time(note 1) t lock - 500 700 ns erase suspend time(note 1) t esp - 400 500 s erase resume time(note 1) 1 block t ers1 -23ms 2~64 blocks t ers2 46ms number of partial program cycles in the sector (including main and spare area) nop - - 2 cycles block erase time (note 1) 1 block t bers1 -23ms 2~64 blocks t bers2 -46ms multi block erase verify read time(note 1) t rd3 - 70 100 s 5.7 ac characteristics for asynchronous write/load/ program/erase operation see timing diagrams 6.7, 6.8 and 6.9
onenand256(kfg5616x1a-xxb6) flash memory 94 6.1 8-word linear burst mode with wrap around see ac characteristics table 5.4 6.2 continuous linear burst mode with wrap around see ac characteristics table 5.4 5 cycles for initial access shown. t ces t avds t avdh t acs t ach t iaa t ba t bdh t clk ce clk avd oe dq0-dq15 a0-a15 d6 d7 d0 d1 d2 d3 d7 t rdya t oe brl=4 t cez t oez d0 t clkh t clkl t rdyo t cer hi-z rdy t rdys hi-z 5 cycles for initial access shown. t ces t avds t avdh t acs t ach t iaa t ba t bdh t clk hi-z ce clk avd oe dq0-dq15 rdy a0-a15 t rdys da da+1 da+2 da+3 da+4 da+5 da+n t rdya t oe brl=4 t cez t oez da+n+1 hi-z t rdyo t cer 6.0 timing diagrams
onenand256(kfg5616x1a-xxb6) flash memory 95 6.4 asynchronous read (va and avd transition after ce low) see ac characteristics table 5.5 note: va=valid read address, rd=read data. t oe va valid rd t ce t oez ce oe we a0-a15 clk v il avd hi-z hi-z rdy t avdp t aavdh dq0-dq15 t cez note: va=valid read address, rd=read data. t oe va valid rd t oez ce oe we a0-a15 clk v il avd t aa hi-z hi-z rdy t avdp t aavdh dq0-dq15 t wea t cez 6.3 asynchronous read (va and avd transition before ce low) see ac characteristics table 5.5
onenand256(kfg5616x1a-xxb6) flash memory 96 6.6 asynchronous read (avd is tied to ce ) see ac characteristics table 5.5 note: va=valid read address, rd=read data. t oe va valid rd t oez ce oe we a0-a15 t acc clk v il avd t aavds hi-z hi-z rdy t avdp t aavdh dq0-dq15 t wea t cez note: va=valid read address, rd=read data. t oe va valid rd t ce t oez ce oe we a0-a15 t acc clk v il hi-z hi-z rdy t rc dq0-dq15 t cez 6.5 asynchronous read (va and avd transition after ce low) see ac characteristics table 5.5
onenand256(kfg5616x1a-xxb6) flash memory 97 note: va=valid read address, wd=write data. ce we oe rp a0-a15 t cs dq0-dq15 valid wd t ds rdy va valid wd t wpl t wph t wc t dh t awes va t ah hi-z hi-z clk v il t ch t cs 6.7 asynchronous write see ac characteristics table 5.7
onenand256(kfg5616x1a-xxb6) flash memory 98 notes: 1. aa = address of address register ca = address of command register lcd = load command lma = address of memory to be loaded ba = address of bufferram to load the data bd = program data sa = address of status register 2. ?in progress? and ?complete? refer to status register 3. status reads in this figure is asynchronous read , but status read in synchronous mode is also supported. load command sequence a0:a15 we ce clk t ds t dh t ch t wpl t cs t wph t wc ca ba ba lcd lma aa dq0-dq15 oe read data v il da da+1 t ah t awes int t rd t ch t cs 6.8 load operation timing see ac characteristics tables 5.7 and 5.8
onenand256(kfg5616x1a-xxb6) flash memory 99 notes: 1. aa = address of address register ca = address of command register pcd = program command pma = address of memory to be programmed ba = address of bufferram to load the data bd = program data sa = address of status register 2. ?in progress? and ?complete? refer to status register 3. status reads in this figure is asynchronous read , but status read in synchronous mode is also supported. program command sequence (last two cycles) a0:a15 we ce clk t ds t dh t ch t wpl t cs t wph t wc sa sa in progress complete aa dq0-dq15 oe read status data v il ba ca pcd pma bd t ah t awes t pgm int t ch t ch t cs t cs 6.9 program operation timing see ac characteristics tables 5.7 and 5.8
onenand256(kfg5616x1a-xxb6) flash memory 100 notes: 1. aa = address of address register ca = address of command register ecd = erase command ema = address of memory to be erased sa = address of status register 2. ?in progress? and ?complete? refer to status register 3. status reads in this figure is asynchronous read, but status read in synchr onous mode is also supported. erase command sequence (last two cycles) a0:a15 we ce t ds t dh t ch ca sa sa in progress complete ecd ema aa dq0-dq15 oe read status data t wpl t cs t wph t wc clk v il t ah t awes t bers int t ch t cs 6.10 block erase operation timing see ac characteristics tables 5.7 and 5.8
onenand256(kfg5616x1a-xxb6) flash memory 101 note: 1) bootcode copy operation starts 400us later than por activation. the system power should reach vcc after por triggering level(typ. 1.5v) within 400us for valid boot code data. for 2.65v and 3.3v device, the system power sh ould reach vcc after por triggering level(typ. 1.8v) within 400us fo r valid boot code data. 2) 1k bytes bootcode copy takes 70us(estimated) from sector0 and sector1/page0/block0 of nand flash array to bootram. host can read bootcode in bootram(1k bytes) after bootcode copy completion. 3) int register goes ?low? to ?high? on the condition of ?bootcode-copy done? and rp rising edge. if rp goes ?low? to ?high? before ?bootcode-copy done?, int register goes to ?low? to ?high? as soon as ?bootcode-copy done? system power sleep bootcode copy idle bootcode - copy done por triggering level 3) 2) rp int onenand operation 0 (default) 1 iobe bit 1 (default) intpol bit high-z 1) int bit 0 (default) 1 6.11 cold reset timing
onenand256(kfg5616x1a-xxb6) flash memory 102 6.12 warm reset timing see ac characteristics tables 5.6 ce , oe rp t rp t ready1 rdy int high-z high-z t ready2 idle 1) operation status reset ongoing 2) bootram access 3) idle 1) int bit polling 4) notes: 1. the status which can accept any register based operation(load, program, erase command, etc). 2. the status where reset is ongoing. 3. the status allows only bootram(bl1) read operation for boot sequence.(refer to 7.2.2 boot sequence) 4. to read bl2 of boot sequence, host should wait int until becomes ready. and then, host can issue load command. (refer to 7.2.2 boot sequence, 7.1 methods of determing interrupt status)
onenand256(kfg5616x1a-xxb6) flash memory 103 6.13 hot reset timing note: 1. internal reset operation means that the device initializes in ternal registers and makes output signals go to default status and bufferram data are kept unchanged after warm/hot reset operations. 2. reset command : command based reset or register based reset 3. bp(boot partition): bootram area [0000h~01ffh, 8000h~800fh] 4. 00f0h for bp, and 00f3h for f220h avd bp(note 3) int a0~a15 we ce or f220h rdy operation or idle onenand reset idle onenand operation high-z dq0~dq15 00f0h or 00f3h 4) oe t ready 2 bit
onenand256(kfg5616x1a-xxb6) flash memory 104 6.15 data protectio n timing during power down v cc rp nand write protected idle one nand reset int onenand operation typ. 1.3v 0v the device is designed to offer protection fr om any involuntary program/erase during pow er-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.3v. rp pin provides hardware protection and is recommended to be kept at v il before power-down. 6.14 nand flash core reset timing avd ce f220h rdy operation or idle nand flash core reset idle onenand operation high-z 00f0h a0~a15 dq0~dq15 int we oe t ready 2 bit
onenand256(kfg5616x1a-xxb6) flash memory 105 from time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a system are included in this section. contact your samsung repr esentative to determine if add itional notes are available. 7.1 methods of determining interrupt status there are two methods of determining interrupt status on the onen and. using the int pin or monitoring the interrupt status regi s- ter bit. the onenand int pin is an output pin function used to notify the host when a command has been completed. this provides a hard- ware method of signaling the completion of a program, erase, or load operation. in its normal state, the int pin is high if the int polarity bi t is default. before a command is written to the command registe r, the int bit must be written to '0' so the int pin transitions to a lo w state indicating start of the operation. upon completion of the command operation by the onenand?s internal controller, int returns to a high state. int is an open drain output allowing multiple int outputs to be or -tied together. int does not float to a hi-z condition when t he chip is deselected or when outputs are disabled. refer to section 2.8 for additional information about int. int can be implemented by tying int to a host gpio or by continuous polling of the interrupt status register. 7.1.1 the int pin to a host general purpose i/o int can be tied to a host gpio to detect the rising edge of int, signaling the end of a command operation. this can be configured to operate either synchronously or asynchronously as s hown in the diagrams below. int command 7.0 technical and application notes
onenand256(kfg5616x1a-xxb6) flash memory 106 synchronous mode using the int pin when operating synchronously, int is tied directly to a host gpio. an alternate method of determining the end of an operation is to continuously monitor the interrupt status register bit instead of using the int pin. host onenand asynchronous mode using the int pin when configured to operate in an asynchronous mode, ce and avd of the onenand are tied to ce of the host. clk is tied to the host vss (ground). rdy is tied to a no-connect. oe of the onenand and host are tied together and int is tied to a gpio. rdy oe clk ce rdy oe clk ce avd avd gpio int host onenand n.c oe vss ce rdy oe clk ce avd gpio int this can be configured in either a sync hronous mode or an asynchronous mode. int command 7.1.2 polling the interrupt register st atus bit
onenand256(kfg5616x1a-xxb6) flash memory 107 synchronous mode using interrupt status register bit polling when operating synchronously, ce , avd , clk, rdy, oe , and dq pins on the host and onenand are tied together. host onenand rdy oe clk ce rdy oe clk ce avd avd dq dq asynchronous mode using interrupt status register bit polling when configured to operate in an asynchronous mode, ce and avd of the onenand are tied to ce of the host. clk is tied to the host vss (ground). rdy is tied to a no-connect. oe and dq of the onenand and host are tied together. host onenand n.c oe ce rdy oe clk ce avd dq dq vss
onenand256(kfg5616x1a-xxb6) flash memory 108 because the pull-up resistor value is related to tr(int) an appr opriate value can obtained with the following reference charts. 7.1.3 determining rp value tr,tf ibusy [ma] rp(ohm) ibusy tr[us] kfg5616x1a @ vcc = 1.8v, t a = 25 c , c l = 30pf 1k 10k 20k 30k 0.089 tf[ns] 0.7727 1.345 1.788 3.77 3.77 3.77 3.77 1.75 0.18 0.09 40k 50k 2.142 2.431 3.77 3.77 0.045 0.06 0.036 open(100k) 5.420 0.000 busy state ready vcc v oh tf tr v ol vss ~50k ohm int vcc and vccq rp int pol = ?high?
onenand256(kfg5616x1a-xxb6) flash memory 109 ~50k ohm int vcc and vccq rp int pol = ?low? tr,tf ibusy [ma] rp(ohm) ibusy tf[us] 1k 10k 20k 30k 0.067 tr[ns] 0.586 1.02 1.356 6.49 6.49 6.49 6.49 1.75 0.18 0.09 40k 50k 1.623 1.84 6.49 6.49 0.045 0.06 0.036 open(100k) 4.05 0.000 busy state ready v oh tf tr v ol vss vcc kfg5616x1a @ vcc = 1.8v, t a = 25 c , c l = 30pf
onenand256(kfg5616x1a-xxb6) flash memory 110 one of the best features onenand has is t hat it can be a booting device itself since it contains an internally built-in boot lo ader despite the fact that its core architecture is based on nand flash. thus, onenand does not make any additional booting device necessary for a system, which imposes extra cost or area overhead on the overall system. as the system power is turned on, the boot code originally stored in nand flash arrary is moved to bootram automatically and th en fetched by cpu through the same interface as sram?s or nor flash? s if the size of the boot code is less than 1kb. if its size i s larger than 1kb and less than or equal to 2kb, only 1kb of it can be mo ved to bootram automatically and fetched by cpu, and the rest o f it can be loaded into one of the datarams w hose size is 1kb by load command and cpu can take it from the dataram after finish- ing the code-fetching job for bootram. if it s size is larger than 2kb, the 1kb portion of it can be moved to bootram automatica lly and fetched by cpu, and its remaining part can be moved to dram through two datarams using dual buffering and taken by cpu to reduce cpu fetch time. a typical boot scheme usually used to boot the system with onenand is explained at patition of nand flash array and onenand boot sequence. in this boot scheme, boot code is comprised of b l1, where bl stands for boot loader, bl2, and bl3. moreover, the size of the boot code is larger than 3kb (the 3rd case above). b l1 is called primary boot loader in other words. here is the ta ble of detailed explanations about the function of eac h boot loader in this specific boot scheme. boot loaders in onenand nand flash array of onenand is divided into the partitions as de scribed at partition of nand flash array to show where each component of code is located and how much portion of the over all nand flash array each one occupies. in addition, the boot sequence is listed below and depicted at boot sequence. boot loader description bl1 moves bl2 from nand flash array to dra m through two datarams using dual buffering bl2 moves os image (or bl3 opt ionally) from nand flash array to dram through two datarams using dual buffering bl3 (optional) moves or writes the image through usb interface 7.2.1 boot loaders in onenand boot sequence : 1. power is on bl1 is loaded into bootram 2. bl1 is executed in bootram bl2 is loaded into dram through two datarams using dual buffering by bl1 3. bl2 is executed in dram os image is loaded into dram through two datarams using dual buffering by bl2 4. os is running 7.2.2 boot sequence 7.2 boot sequence
onenand256(kfg5616x1a-xxb6) flash memory 111 reservoir file system os image bl2 bl1 os image bl 2 nand flash array onenand dram onenand boot sequence internal bufferram data ram 1 data ram 0 boot ram(bl 1) note : step 2 and step 3 can be copied into dram through two datarams using dual buffering step 1 step 2 step 3 reservoir file system os image nbl3 nbl2 nbl1 partition 6 block 162 block 2 block 1 block 0 partition 5 sector 0 sector 1 bl2 partition 4 partition 3 partition of nand flash array reservoir file system os image bl3 bl2 bl1 partition 6 block 162 block 2 block 1 block 0 partition 5 sector 0 sector 1 page 63 page 62 page 2 page 1 page 0 partition 4 partition 3 : : bl1 block 512
onenand256(kfg5616x1a-xxb6) flash memory 112 8.0 package dimensions 256mb product (kfg5616x1a) 67-fbga-7.00x9.00 units:millimeters 0.10 max 0.45 0.05 0.32 0.05 0.90 0.10 bottom view top view 0.80x7=5.60 a 0.80x9=7.20 67- ? 0.45 0.05 0 . 8 0 b 0.20 m a b ? (datum a) (datum b) #a1 index 7.00 0.10 9.00 0.10 #a1 9.00 0.10 7.00 0.10 9.00 0.10 b d a c e f g h 1 432 5 6 0.80 2.800 3 . 6 0
onenand256(kfg5616x1a-xxb6) flash memory 113 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 256mb product (kfg5616x1a)

▲Up To Search▲

Price & Availability of KFG5616Q1A-PEB6

	To Download KFG5616Q1A-PEB6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .